參數(shù)資料
型號(hào)： ADRF6801ACPZ-R7
廠商： ANALOG DEVICES INC
元件分類： 調(diào)制器/解調(diào)器
英文描述： 750 MHz - 1150 MHz RF/MICROWAVE I/Q DEMODULATOR
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, CP-40-1, LFSCP_VQ, 40 PIN
文件頁(yè)數(shù)： 35/36頁(yè)
文件大小： 1034K
代理商： ADRF6801ACPZ-R7
ADRF6801
Rev. 0 | Page 8 of 36
Pin No.
Mnemonic
Description
5
RSET
Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1
mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this
mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents
(INOMINAL) can be externally tweaked according to the following equation where the resulting value is in
units of ohms.
8
.
37
4
.
217
×
=
NOMINAL
CP
SET
I
R
6
REFIN
Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz.
8
MUXOUT
Multiplexer Output. This output can be programmed to provide the reference output signal or
the lock detect signal. The output is selected by programming the appropriate register.
9
DECL2
Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground.
10
VCC2
The 5 V power supply pin for the 2.5 V LDO.
12
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
13
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
14
LE
Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into
one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit
word.
17, 34
VCCLO
The 5 V Power Supply for the LO Path Blocks.
18, 19
QBBP, QBBN
Demodulator Q-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω.
22, 29
VCCBB
The 5 V Power Supply for the Baseband Output Section of the Demodulator Blocks.
25
GNDRF
Ground Return for RF Input Balun.
26
RFIN
Single-Ended, Ground Referenced 50 Ω, RF Input.
27
VCCRF
The 5 V Power Supply for the RF Input Section of the Demodulator Blocks.
32, 33
IBBN, IBBP
Demodulator I-Channel Differential Baseband Outputs; Differential Output Impedance of 24 Ω.
36
LOSEL
LO Select. Connect this pin to ground for the simplest operation and to completely control the LO
path and input/output direction from the register SPI programming.
For additional control without register reprogramming, this input pin can determine whether the
LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is
set low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The
externally applied LO drive must be at 2×LO frequency (and the LDIV bit of Register 5 (DB5) set
low). LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set
high and the LXL bit of Register 5 (DB4) is set low. The output frequency is 2×LO frequency (and
the LDIV bit of Register 5 (DB5) must be set high). This pin should not be left floating.
37, 38
LON, LOP
Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency
divided version of the internal VCO is available on these pins. When the internal LO generation is
disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds
to the LO path divider setting). (Differential Input/Output Impedance of 50 Ω)
39
VTUNE
VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input
voltage range on this pin is 1.0 V to 2.8 V.
40
DECL1
Connect a 10 μF capacitor between this pin and ground as close to the device as possible
because this pin serves as the VCO supply and loop filter reference.
EP
Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
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