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參數(shù)資料
| 型號： | ADRF6801ACPZ-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 調(diào)制器/解調(diào)器 |
| 英文描述： | 750 MHz - 1150 MHz RF/MICROWAVE I/Q DEMODULATOR |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, CP-40-1, LFSCP_VQ, 40 PIN |
| 文件頁數(shù)： | 6/36頁 |
| 文件大?。?/td> | 1034K |
| 代理商： | ADRF6801ACPZ-R7 |
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ADRF6801
Rev. 0 | Page 14 of 36
CIRCUIT DESCRIPTION
The ADRF6801 integrates a high performance IQ demodulator
with a state-of-the-art fractional-N PLL. The PLL also integrates
a low noise VCO. The SPI port allows the user to control the
fractional-N PLL functions, the demodulator LO divider functions,
and optimization functions, as well as allowing for an externally
applied LO.
The ADRF6801 uses a high performance mixer core that results
in an exceptional input IP3 and input P1dB, with a very low output
noise floor for excellent dynamic range.
LO QUADRATURE DRIVE
A signal at 2× the desired mixer LO frequency is delivered to
a divide-by-2 quadrature phase splitter followed by limiting
amplifiers which then drive the I and Q mixers, respectively.
V-TO-I CONVERTER
The RF input signal is applied to an on-chip balun which then
provides both a ground referenced, 50 Ω single-ended input
impedance and a differential voltage output to a V-to-I converter
that converts the differential voltages to differential output currents.
These currents are then applied to the emitters of the Gilbert
cell mixers.
MIXERS
The ADRF6801 has two double-balanced mixers: one for the
in-phase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistive loads that
then feed into the subsequent emitter follower buffers.
EMITTER FOLLOWER BUFFERS
The output emitter followers drive the differential I and Q signals
off chip. The output impedance is set by on-chip 12 Ω series
resistors that yield a 24 Ω differential output impedance for each
baseband port. The fixed output impedance forms a voltage divider
with the load impedance that reduces the effective gain. For example,
a 500 Ω differential load has ~0.5 dB lower effective gain than
with a high (10 kΩ) differential load impedance.
The common-mode dc output levels of the emitter followers are set
from VCCBB via the voltage drop across the mixer load resistors,
the VBE of the output emitter follower, and the voltage drop
across the 12 Ω series resistor.
BIAS CIRCUITRY
There are several band gap reference circuits and three low
dropout regulators (LDOs) in the ADRF6801 that generate the
reference currents and voltages used by different sections. The
first of the LDOs is the 2.5 V LDO, which is always active and
provides the 2.5 V supply rail used by the internal digital logic
blocks. The 2.5 V LDO output is connected to DECL2 (Pin 9)
for the user to provide external decoupling.
The second LDO is the VCO LDO, which acts as the positive
supply rail for the internal VCO. The VCO LDO output is
connected to DECL2 (Pin 40) for the user to provide external
decoupling. The VCO LDO can be powered down by setting
Register 6, DB18 = 0, which allows the user to save power when
not using the VCO.
The third LDO is the 3.3 V LDO, which acts as the 3.3 V
positive supply rail for the reference input, phase frequency
detector, and charge pump circuitry. The 3.3 V LDO output is
connected to DECL3 (Pin 2) for the user to provide external
decoupling. The 3.3 V LDO can be powered down by setting
Register 6, DB19 = 0, which allows the user to save power when
not using the VCO. The demodulator also has a bias circuit that
supplies bias current for the mixer V-to-I stage, which then sets
the bias for the mixer core. The demodulator bias cell can also
be shut down by setting Register 5, DB7 = 0.
REGISTER STRUCTURE
The ADRF6801 provides access to its many programmable
features through a 3-wire SPI control interface that is used to
program the seven internal registers. The minimum delay and
hold times are shown in the timing diagram (see Figure 2). The
SPI provides digital control of the internal PLL/VCO as well as
several other features related to the demodulator core, on-chip
referencing, and available system monitoring functions. The
MUXOUT pin provides a convenient, single-pin monitor output
signal that can be used to deliver a PLL lock-detect signal or an
internal voltage proportional to the local junction temperature.
Note that internal calibration for the PLL must run when the
ADRF6801 is initialized at a given frequency. This calibration is run
automatically whenever Register 0, Register 1, or Register 2 is
programmed. Because the other registers affect PLL performance,
Register 0, Register 1, and Register 2 must always be programmed
last. For ease of use, starting the initial programming with
Register 7 and then programming the registers in descending
order, ending with Register 0, is recommended. Once the PLL
and other settings are programmed, the user can change the
PLL frequency simply by programming Register 0, Register 1,
or Register 2 as necessary.
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| ADRF6801-EVALZ | 功能描述:EVAL BOARD FOR ADRF6801 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 類型:解調(diào)器 頻率:750MHz ~ 1.15GHz 配套使用產(chǎn)品/相關(guān)產(chǎn)品:ADRF6801 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| ADRF6806ACPZ-R7 | 功能描述:IC QUADRATURE DEMOD 40LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 解調(diào)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 功能:解調(diào)器 LO 頻率:- RF 頻率:70MHz ~ 300MHz P1dB:-9dBm 增益:- 噪音數(shù)據(jù):6.36dB 電流 - 電源:41.5mA 電源電壓:2.7 V 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ADRF6806-EVALZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:EVAL 525MHZ QUAD DEMOD ADRF6806 制造商:Analog Devices 功能描述:ADRF6806, QUAD DEMOD, EVAL BOARD; Silicon Manufacturer:Analog Devices; Features:IQ Demodulator with Integrated Fractional-N PLL, Integrated PLL & VCO; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: Yes 制造商:Analog Devices 功能描述:MODULATOR/DEMODULATOR |
| ADRF6807 | 制造商:AD 制造商全稱:Analog Devices 功能描述:700 MHz to 1050 MHz Quadrature |
| ADRF6807ACPZ-R7 | 功能描述:IC QUADRATURE DEMOD 40LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 解調(diào)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 功能:解調(diào)器 LO 頻率:- RF 頻率:70MHz ~ 300MHz P1dB:-9dBm 增益:- 噪音數(shù)據(jù):6.36dB 電流 - 電源:41.5mA 電源電壓:2.7 V 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-TQFN-EP（5x5） 包裝:帶卷 (TR) |
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