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參數(shù)資料
| 型號(hào)： | ADRF6704ACPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 調(diào)制器/解調(diào)器 |
| 英文描述： | 2500 MHz - 2900 MHz RF/MICROWAVE I/Q MODULATOR |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP_VQ, CP-40-1, 40 PIN |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 581K |
| 代理商： | ADRF6704ACPZ |
Preliminary Technical Data
ADRF6704
REGISTER 5 LO PATH AND MODULATOR CONTROL
The modulator output or the complete modulator can be
disabled using the modulator bias enable and modulator
output enable addresses of register 5.
The LO port (pins LOP and LON) can be used to apply an
external 2X LO (i.e. bypass internal PLL) to the IQ Modulator.
A differential LO drive of 0 dBm is recommended for best LO
suppression at the RF output. When using an external
frequency stable local oscillator signal to commutate the mixer
core it is possible to shut down the PLL circuitry through the
PLL enable address of register 5.
The LO port can also be used as an output where a 2X or 1X LO
can be brought out and used to drive another mixer. The
nominial output power provided at the LO port is +3 dBm.
The LO port’s mode of operation is determined by the status of
the LOSEL pin (3.3 V logic) along with the settings in a number
of internal registers.
Table 6. LO Port Configuration
LON/LOP
Function
LOSEL
R5:DB3
(LDRV)
R5:DB5
(LDIV)
R5:DB4(LXL)
Input (2XLO)
0
X
1
Output (1XLO)
X
1
0
X
Output (1XLO)
1
X
0
X
Output (2XLO)
X
1
X
Output (2XLO)
1
X
1
X
X = Don’t Care
The device’s internal VCO can also be bypassed. In this case,
the charge pump output drives an external VCO through the
loop filter. The loop is completed by routing the VCO in to the
device through the LO Port.
LDRV
LO Output
Driver Enable
0
Driver Off (default)
1
Driver
O
n
LXL
LO In/Out
Control
0
LO Output (default)
1
LO
I
nput
Mod
Bias
Enable
RF
Output
Enable
LO
Output
Divider
LO
In/Out
Control
LO
Output
Driver
Enable
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
0
MBE
RFEN
LDIV
LXL
LDRV
LDIV
LO Output Divide Mode
0
Divide by 1
1
Divide by 2 (default)
RFEN
RF Output Enable
0
Disable
1
Enable (default)
MBE
Mod Bias Enable
0
Disable
1
Enable
(
default)
LDRV
LO Output
Driver Enable
0
Driver Off (default)
1
Driver
O
n
LXL
LO In/Out
Control
0
LO Output (default)
1
LO
I
nput
Mod
Bias
Enable
RF
Output
Enable
LO
Output
Divider
LO
In/Out
Control
LO
Output
Driver
Enable
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
MBE
RFEN
LDIV
LXL
LDRV
C3(1)
C2(0)
C1(1)
Control Bits
LDIV
LO Output Divide Mode
0
Divide by 1
1
Divide by 2 (default)
RFEN
RF Output Enable
0
Disable
1
Enable (default)
MBE
Mod Bias Enable
0
Disable
1
Enable
(
default)
Figure 10. LO Path and Modulator Control (R5)
Rev. PrE | Page 15 of 18
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