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參數(shù)資料
| 型號： | ADRF6704ACPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 調(diào)制器/解調(diào)器 |
| 英文描述： | 2500 MHz - 2900 MHz RF/MICROWAVE I/Q MODULATOR |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP_VQ, CP-40-1, 40 PIN |
| 文件頁數(shù)： | 5/18頁 |
| 文件大小： | 581K |
| 代理商： | ADRF6704ACPZ |
Preliminary Technical Data
ADRF6704
REGISTER 4—CHARGE PUMP, PFD AND
REFERENCE PATH CONTROL
With R4[2:0] set to 100, the on-chip Charge Pump, PFD and
Reference Path Control register is programmed as shown in
figure 43.
The charge pump current is controlled by the base charge pump
current (ICP,BASE), and the value of the charge pump current
multiplier (ICP,MULT).
The base charge pump current can be set using an internal or
external resistor (according to DB18 of Register 4). When using
an external resistor, the value of ICP,BASE can be varied according
to the following table.
217 .4 × I
CP ,BASE
R
SET []
Ω =
37 .8
250
The actual charge pump current can be programmed to be a
multiple (1, 2, 3, 4) of the charge pump base current. The
multiplying value (ICP,MULT) is equal to 1 plus the value of bits
DB11 and DB10 in register 4.
The PFD phase offset multiplier (θPFD,OFS), which is set by bits
DB16-DB12 of Register 4, will cause the PLL to lock with a
nominally fixed phase offset between the PFD reference signal
and the divided-down VCO signal. This phase offset is used to
linearize the PFD-CP transfer function and can improve
fractional spurs. The magnitude of the phase offset is
determined by the following equation:
θ
PFD ,OFS
ΔΦ [deg] = 22 .5
I
CP , MULT
Finally, the phase offset can be either positive or negative
depending on the value of DB17 in register 4.
The reference frequency applied to the PFD can be manipulated
using the internal reference path source. The external reference
frequency applied can be internally scaled in frequency by 2X,
1X, 0.5X, or 0.25X. This allows a broader range of reference
frequency selections while keeping the reference frequency
applied to the PFD within an acceptable range.
The ADRF6704 also provides a MUXOUT pin that can be
programmed to output a selection of several internal signals.
The default mode is to provide a lock-detect output to allow the
user to verify when the PLL has locked to the target frequency.
In addition, several other internal signals may be passed to the
MUXOUT pin as described in figure 43.
Rev. PrE | Page 13 of 18
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| ADRF6704ACPZ-R7 | 功能描述:IC MOD QUAD FRAC N PLL 40LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 調(diào)制器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 功能:調(diào)制器 LO 頻率:700MHz ~ 2.3GHz RF 頻率:700MHz ~ 2.3GHz P1dB:1dBm 底噪:-148dBm/Hz 輸出功率:-1dBm 電流 - 電源:46mA 電源電壓:2.7 V ~ 3.6 V 測試頻率:1.75GHz 封裝/外殼:28-WFQFN 裸露焊盤 包裝:帶卷 (TR) |
| ADRF6704-EVALZ | 制造商:Analog Devices 功能描述:EVAL QUAD MODULATOR ADRF6704 制造商:Analog Devices 功能描述:ADRF6704, QUAD MODULATOR, EVAL BOARD |
| ADRF6720-27ACPZ-R7 | 功能描述:RF Modulator IC 400MHz ~ 3GHz 40-WFQFN Exposed Pad, CSP 制造商:analog devices inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 功能:調(diào)制器 LO 頻率:356MHz ~ 2.855GHz RF 頻率:400MHz ~ 3GHz P1dB:11dBm 本底噪聲:-162dBm/Hz 輸出功率:5dBm 電流 - 電源:425mA 電壓 - 電源:3.3V 測試頻率:2.14GHz 封裝/外殼:40-WFQFN 裸露焊盤，CSP 標準包裝:1 |
| ADRF6720-27-EVALZ | 功能描述:EVAL BOARD FOR ADRF6720-27 制造商:analog devices inc. 系列:- 零件狀態(tài):有效 類型:調(diào)制器 頻率:400MHz ~ 3GHz 配套使用產(chǎn)品/相關(guān)產(chǎn)品:ADRF6720-27 所含物品:板 標準包裝:1 |
| ADRF6720ACPZ-R7 | 功能描述:WIDEBAND INTEG MOD WITH PLL AND 制造商:analog devices inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 功能:調(diào)制器 LO 頻率:356MHz ~ 2.855GHz P1dB:12.2dBm 本底噪聲:-158dBm/Hz 輸出功率:5dBm 電流 - 電源:425mA 電壓 - 電源:3.3V 測試頻率:2GHz 封裝/外殼:40-WFQFN 裸露焊盤 標準包裝:1 |
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