Register access to the ADP5585 is acquired via its I
參數(shù)資料
型號(hào)： ADP5585CP-EVALZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/40頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADP5585CP
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，GPIO 擴(kuò)展器
已用 IC / 零件： ADP5585
主要屬性： 10 個(gè)可配置的 I/O
次要屬性： I²C 接口
已供物品： 板
Data Sheet
ADP5585
Rev. C | Page 15 of 40
REGISTER INTERFACE
Register access to the ADP5585 is acquired via its I2C-compatible
serial interface. The interface can support clock frequencies of
up to 1 MHz. If the user is accessing the FIFO or key event
counter (KEC), FIFO/KEC updates are paused. If the clock
frequency is very low, events may not be recorded in a timely
manner. FIFO or KEC updates can happen up to 23 μs after an
interrupt is asserted because of the number of I2C cycles required
to perform an I2C read or write. This delay should not present
an issue to the user.
Figure 23 shows a typical write sequence for programming an
internal register. The cycle begins with a start condition, followed
by the hard coded 7-bit device address, which for the ADP5585
is 0x34, followed by the R/W bit set to 0 for a write cycle. The
ADP5585 acknowledges the address byte by pulling the data
line low. The address of the register to which data is to be written
is sent next. The ADP5585 acknowledges the register pointer
byte by pulling the data line low. The data byte to be written is
sent next. The ADP5585 acknowledges the data byte by pulling
the data line low. A stop condition completes the sequence.
Figure 24 shows a typical multibyte write sequence for program-
ming internal registers. The cycle begins with a start condition
followed by the 7-bit device address (0x34 for all models except
the ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7
only), followed by the R/W bit set to 0 for a write cycle. The
ADP5585 acknowledges the address byte by pulling the data
line low. The address of the register to which data is to be written
is sent next. The ADP5585 acknowledges the register pointer
byte by pulling the data line low. The data byte to be written is
sent next. The ADP5585 acknowledges the data byte by pulling
the data line low. The pointer address is then incremented to
write the next data byte, until it finishes writing the n data byte.
The ADP5585 pulls the data line low after every byte, and a stop
condition completes the sequence.
Figure 25 shows a typical byte read sequence for reading inter-
nal registers. The cycle begins with a start condition followed
by the 7-bit device address (0x34 for all models except the
ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7
only), followed by the R/W bit set to 0 for a write cycle. The
ADP5585 acknowledges the address byte by pulling the data line
low. The address of the register from which data is to be read is
sent next. The ADP5585 acknowledges the register pointer byte
by pulling the data line low. A start condition is repeated,
followed by the 7-bit device address (0x34 for all models except
the ADP5585ACPZ-03-R7, 0x30 for the ADP5585ACPZ-03-R7
only), followed by the R/W bit set to 1 for a read cycle. The
ADP5585 acknowledges the address byte by pulling the data
line low. The 8-bit data is then read. The host pulls the data line
high (no acknowledge), and a stop condition completes the
sequence.
START
0 = WRITE
7-BIT DEVICE ADDRESS
ADP5585 ACK
8-BIT REGISTER POINTER
8-BIT WRITE DATA
0
000
ADP5585 ACK
STOP
09
84
1-
02
2
Figure 23. I2C Single Byte Write Sequence
START
0 = WRITE
7-BIT DEVICE ADDRESS
ADP5585 ACK
8-BIT REGISTER POINTER
WRITE BYTE 1
WRITE BYTE 2
WRITE BYTE n
00
0
ADP5585 ACK
STOP
09
84
1-
02
3
Figure 24. I2C Multibyte Write Sequence
START
0 = WRITE
7-BIT DEVICE ADDRESS
ADP5585 ACK
8-BIT REGISTER POINTER
8-BIT READ DATA
00
0
1
0
1
REPEAT START
1 = READ
ADP5585 ACK
NO ACK
STOP
09
84
1-
02
4
Figure 25. I2C Single Byte Read Sequence
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