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參數(shù)資料
| 型號(hào)： | ADP5585CP-EVALZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADP5585CP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，GPIO 擴(kuò)展器 |
| 已用 IC / 零件： | ADP5585 |
| 主要屬性： | 10 個(gè)可配置的 I/O |
| 次要屬性： | I²C 接口 |
| 已供物品： | 板 |
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Data Sheet
ADP5585
Rev. C | Page 9 of 40
FUNCTIONAL DESCRIPTION
EVENT FIFO
Before going into detail on the various ADP5585 blocks, it is
important to understand the function of the event FIFO. The
ADP5585 features an event FIFO that can record as many as 16
events. By default, the FIFO primarily records key events, such as
key press and key release. However, it is possible to configure
the general-purpose input (GPI) and logic activity to generate
event information on the FIFO as well. An event count, EC[4:0],
is composed of five bits and works in tandem with the FIFO so
that the user knows how much of the FIFO must be read back at
any given time.
The FIFO is composed of 16 eight-bit sections that the user
accesses by reading the FIFO_x registers. The actual FIFO is
not in user accessible registers until a read occurs. The FIFO
can be thought of as a “first in first out” buffer that is used to
fill Register 0x03 to Register 0x12.
The event FIFO is made up of 16 eight-bit registers. In each
register, Bits[6:0] hold the event identifier, and Bit 7 holds the
event state. With seven bits, 127 different events can be identified.
See Table 11 for event decoding.
EVENT1[7:0]
EVENT8_IDENTIFIER[6:0]
EVENT2[7:0]
EVENT3[7:0]
EVENT4[7:0]
EVENT13[7:0]
EVENT14[7:0]
EVENT15[7:0]
EVENT16[7:0]
EVENT5[7:0]
EVENT6[7:0]
EVENT7[7:0]
EVENT8[7:0]
EVENT9[7:0]
EVENT10[7:0]
EVENT11[7:0]
EVENT12[7:0]
7
EVENT8_STATE
GPI EVENTS
EC[4:0]
OVRFLOW_INT
KEY EVENTS
LOGIC EVENTS
6
5
4
3
2
1
0
09841-
006
FIFO
UPDATE
Figure 7. Breakdown of Eventx[7:0] Bits
When events are available on the FIFO, the user should first
read back the event count, EC[4:0], to determine how many
events must be read back. Events can be read from the top of
the FIFO only. When an event is read back, all remaining events
in the FIFO are shifted up one location, and the EC[4:0] count
is decremented.
KEY 3 PRESSED
KEY 3 RELEASED
GPI 7 ACTIVE
EC = 3
KEY 3 RELEASED
GPI 7 ACTIVE
EC = 2
GPI 7 ACTIVE
EC = 1
EC = 0
09841-
007
THIRD
READ
SECOND
READ
FIRST
READ
Figure 8. FIFO Operation
The FIFO registers (0x03 to 0x12) always point to the top of the
FIFO (that is, the location of EVENT1[7:0]). If the user tries to
read back from any location in a FIFO, data is always obtained
from the top of that FIFO. This ensures that events can only be
read back in the order in which they occurred, thus ensuring
the integrity of the FIFO system.
As stated above, some of the onboard functions of ADP5585
can be programmed to generate events on the FIFO. A FIFO
update control block manages updates to the FIFO. If an I2C
transaction is accessing any of the FIFO address locations,
updates are paused until the I2C transaction has completed.
A FIFO overflow event occurs when more than 16 events are
generated prior to an external processor reading a FIFO and
clearing it.
If an overflow condition occurs, the overflow status bit is set.
An interrupt is generated if overflow interrupt is enabled,
signaling to the processor that more than 16 events have
occurred.
KEY SCAN CONTROL
General
The 10 input/output pins can be configured to decode a keypad
matrix up to a maximum size of 25 switches (5 × 5 matrix). Smaller
matrices can also be configured, freeing up the unused row and
column pins for other I/O functions.
The R0 through R4 I/O pins comprise the rows of the keypad
matrix. The C0 through C4 I/O pins comprise the columns of
the keypad matrix. Pins used as rows are pulled up via the internal
300 kΩ (or 100 kΩ) resistors. Pins used as columns are driven
low via the internal NMOS current sink.
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| ADP5586 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Keypad Decoder and I/O Port Expander |
| ADP5586ACBZ-00-R7 | 功能描述:接口-I/O擴(kuò)展器 RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
| ADP5586ACBZ-01-R7 | 功能描述:接口-I/O擴(kuò)展器 RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
| ADP5586ACBZ-03-R7 | 功能描述:接口-I/O擴(kuò)展器 RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數(shù)量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
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