參數(shù)資料
型號(hào)： ADP3522ACP-1.8
廠商： ANALOG DEVICES INC
元件分類： 電源管理
英文描述： GSM Power Management System
中文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32
封裝： 5 X 5 MM, EXPOSED PAD, MO-220-VHHD-2, LFCSP-32
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 467K
代理商： ADP3522ACP-1.8
REV. 0
–16–
ADP3522
HIGH CURRENT
3.2V
LOW CURRENT
4.2V
EOC CURRENT
EOC
INDICATOR
I
CHARGE
0
V
BAT
Figure 6. Lithium Ion Charging Diagram
Lithium Ion Charging
For lithium ion charging, the
CHGEN
input must be low. This
allows the ADP3522 to continue charging the battery at the full
current. The full charge current can be calculated by using
I
mV
R
CHR FULL
(
SENSE
)
=
160
(3)
If the voltage at BATSNS is below the charger’s output voltage
of 4.2 V, the battery will continue to charge in the constant
current mode. If the battery has reached the final charge volt-
age, a constant voltage is applied to the battery until the charge
current has reduced to the charge termination threshold. The
charge termination threshold is determined by the voltage across
the sense resistor. If the battery voltage is above 4.0 V and the
voltage across the sense resistor has dropped to 14 mV, then an
end of charge signal is generated—the EOC output goes high
(see Figure 6).
The baseband processor can either let the charger continue to
charge the battery for an additional amount of time or terminate
the charging. To terminate the charging, the processor must
pull the GATEIN pin high and the
CHGEN
pin high.
NiMH Charging
For NiMH charging, the processor must pull the
CHGEN
pin
high. This disables the internal Li+ mode control of the gate
drive pin. The gate drive must now be controlled by the
baseband processor. By pulling GATEIN high, the GATEDR
pin is driven high, turning the PMOS off. By pulling the
GATEIN pin low, the GATEDR pin is driven low, and the
PMOS is turned on. So, by pulsing the GATEIN input, the
processor can charge a NiMH battery. Note that when charging
NiMH cells, a current limited adapter is required.
During the PMOS off periods, the battery voltage needs to be
monitored through the MVBAT pin. The battery voltage is con-
tinually polled until the final battery voltage is reached. Then the
charge can either be terminated or the frequency of the pulsing
reduced. An alternative method of determining the end of charge
is to monitor the temperature of the cells and terminate the
charging when a rapid rise in temperature is detected.
Battery Voltage Monitoring
The battery voltage can be monitored at MVBAT during charg-
ing and discharging to determine the condition of the battery. An
internal resistor divider can be connected to BATSNS when both
the digital and analog baseband sections are powered up. To
enable MVBAT, both PWRONIN and TCXOEN must be high.
The ratio of the voltage divider is selected so that the 2.4 V
maximum input of the AD6521’s auxiliary ADC will corre-
spond with the maximum battery voltage of 5.5 V. The divider
will be disconnected from the battery when the baseband sec-
tions are powered down.
APPLICATION INFORMATION
Input Capacitor Selection
For the input (VBAT, VBAT2, and VRTCIN) of the
ADP3522, a
local bypass capacitor is recommended; use a 10
μ
F, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size but may not be
cost effective. A lower cost alternative may be to use a 10
μ
F
tantalum capacitor with a small (1
μ
F to 2
μ
F) ceramic in parallel.
Separate inputs for the SIM LDO and the RTC LDO are sup-
plied for additional bypassing or filtering. The SIM LDO has
VBAT2 as its input and the RTC LDO has VRTCIN.
LDO Capacitor Selection
The performance of any LDO is a function of the output capacitor.
The core, memory, SIM, and analog LDOs require a 2.2
μ
F
capacitor and the TCXO LDO requires a 0.22
μ
F capacitor.
Larger values may be used, but the overshoot at startup will
increase slightly. If a larger output capacitor is desired, be
sure to check that the overshoot and settling time are accept-
able for the application.
All the LDOs are stable with a wide range of capacitor types and
ESR (anyCAP
technology). The ADP3522 is stable with
extremely low ESR capacitors (ESR ~ 0) such as multilayer
ceramic capacitors (MLCC), but care should be taken in their
selection. Note that the capacitance of some capacitor types
shows wide variations over temperature or with dc voltage. A
good quality dielectric, X7R or better, capacitor is recommended.
The RTC LDO can have a rechargeable coin cell or an electric
double-layer capacitor as a load, but an additional 0.1
μ
F ceramic
capacitor is recommended for stability and best performance.
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