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參數(shù)資料
| 型號(hào)： | ADP3417 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Secondary Over-Voltage Protection for 2-4 cell in series Li-Ion/Poly (4.35V) 8-SM8 -40 to 110 |
| 中文描述： | 雙舉MOSFET驅(qū)動(dòng)電路 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 1487K |
| 代理商： | ADP3417 |
REV. A
ADP3417
–6–
THEORY OF OPERATION
The ADP3417 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high side and the low side FETs. Each driver
is capable of driving a 3 nF load.
A more detailed description of the ADP3417 and its features
follows. Refer to the Functional Block Diagram.
Low Side Driver
The low side driver is designed to drive low R
DS(ON)
N-channel
MOSFETs. The maximum output resistance for the driver is
3
for sourcing and 2.5
for sinking gate current. The low
output resistance allows the driver to have 25 ns rise times
and 20 ns fall times into a 3 nF load. The bias to the low side
driver is internally connected to the VCC supply and PGND.
When the driver is enabled, the driver
’
s output is 180 degrees
out of phase with the PWM input. When the ADP3417 is dis-
abled, the low side gate is held low.
High Side Driver
The high side driver is designed to drive a floating low R
DS(ON)
N-channel MOSFET. The maximum output resistance for the
driver is 3
for sourcing and 2.5
for sinking gate current.
The low output resistance allows the driver to have 45 ns rise times
and 20 ns fall times into a 3 nF load. The bias voltage for the
high side driver is developed by an external bootstrap supply
circuit, which is connected between the BST and SW Pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, C
BST
. When the ADP3417 is starting up, the SW Pin
is at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high side
driver will begin to turn the high side MOSFET, Q1, ON by
pulling charge out of C
BST
. As Q1 turns ON, the SW Pin will
rise up to V
IN
, forcing the BST Pin to V
IN
+ V
C(BST)
, which is
enough gate to source voltage to hold Q1 ON. To complete the
cycle, Q1 is switched OFF by pulling the gate down to the volt-
age at the SW Pin. When the low side MOSFET, Q2, turns
ON, the SW Pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again. The high side driver
’
s
output is in phase with the PWM input.
Overlap Protection Circuit
The overlap protection circuit (OPC) prevents both of the main
power switches, Q1 and Q2, from being ON at the same time.
This is done to prevent shoot-through currents from flowing
through both power switches and the associated losses that can
occur during their ON-OFF transitions. The overlap protection
circuit accomplishes this by adaptively controlling the delay from
Q1
’
s turn OFF to Q2
’
s turn ON and by internally setting the
delay from Q2
’
s turn OFF to Q1
’
s turn ON.
To prevent the overlap of the gate drives during Q1
’
s turn OFF
and Q2
’
s turn ON, the overlap circuit monitors the voltage at the
SW Pin. When the PWM input signal goes low, Q1 will begin to
turn OFF (after a propagation delay), but before Q2 can turn ON,
the overlap protection circuit waits for the voltage at the SW Pin
to fall from V
IN
to 1 V. Once the voltage on the SW Pin has fallen
to 1 V, Q2 will begin turn ON. By waiting for the voltage on the
SW Pin to reach 1 V, the overlap protection circuit ensures that
Q1 is OFF before Q2 turns on, regardless of variations in tem-
perature, supply voltage, gate charge, and drive current.
To prevent the overlap of the gate drives during Q2
’
s turn OFF
and Q1
’
s turn ON, the overlap circuit provides a internal delay
that is set to 50 ns. When the PWM input signal goes high, Q2
will begin to turn OFF (after a propagation delay), but before
Q1 can turn ON, the overlap protection circuit waits for the
voltage at DRVL to drop to around 10% of VCC. Once the
voltage at DRVL has reached the 10% point, the overlap protec-
tion circuit will wait for a 50 ns typical propagation delay. Once
the delay period has expired, Q1 will begin turn ON.
APPLICATION INFORMATION
Supply Capacitor Selection
For the supply input (VCC) of the ADP3417, a local bypass
capacitor is recommended to reduce the noise and to supply some
of the peak currents drawn. Use a 1
μ
F, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size. Keep the ceramic capacitor
as close as possible to the ADP3417.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (C
BST
) and a
diode, as shown in Figure 1. Selection of these components can
be done after the high side MOSFET has been chosen.
The bootstrap capacitor must have a voltage rating that is able
to handle the maximum supply voltage. A minimum 25 V rating
is recommended. The capacitance is determined using the
following equation:
C
Q
V
BST
GATE
BST
=
(1)
where,
Q
GATE
is the total gate charge of the high side MOSFET,
and
V
BST
is the voltage droop allowed on the high side MOSFET
drive. For example, the IRF7811 has a total gate charge of about
20 nC. For an allowed droop of 200 mV, the required boot-
strap capacitance is 100 nF. A good quality ceramic capacitor
should be used.
A small-signal diode can be used for the bootstrap diode due to
the ample gate drive available for the high side MOSFET. The
bootstrap diode must have a minimum 15 V rating to withstand
the maximum boosted supply voltage. The average forward
current can be estimated by:
I
Q
f
F(AVG)
GATE
MAX
≈
×
(2)
where
f
MAX
is the maximum switching frequency of the control-
ler. The peak surge current rating should be checked in-circuit,
since this is dependent on the source impedance of the 12 V
supply and the ESR of C
BST
.
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
1. Trace out the high current paths and use short, wide traces
to make these connections.
2. Connect the PGND Pin of the ADP3417 as close as possible
to the source of the lower MOSFET.
3. The VCC bypass capacitor should be located as close as
possible to VCC and PGND Pins.
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