- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223311 > ADP1875ARQZ-0.3-R7 (ANALOG DEVICES INC) SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, PDSO16 PDF資料下載
參數(shù)資料
| 型號(hào)： | ADP1875ARQZ-0.3-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | ROHS COMPLIANT, MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 32/44頁 |
| 文件大?。?/td> | 2475K |
| 代理商： | ADP1875ARQZ-0.3-R7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
ADP1874/ADP1875
Rev. 0 | Page 38 of 44
09
34
7-
09
5
BOTTOM
RESISTOR TAP
TO ANALOG
GROUND PLANE
PGND SENSE TAP FROM
NEGATIVE TERMINALS OF
THE OUTPUT BULK
CAPACITORS. THIS
TRACK PLACEMENT
SHOULD BE DIRECTLY
BELOW THE VOUT SENSE
LINE OF LAYER 3.
Figure 94. Layer 4 (Bottom Layer) of Evaluation Board
The SW node is near the top of the evaluation board. The SW
node should use the least amount of area possible and be away
from any sensitive analog circuitry and components. This is
because the SW node is where most sudden changes in flux
density occur. When possible, replicate this pad onto Layer 2
and Layer 3 for thermal relief and eliminate any other voltage and
current pathways directly beneath the SW node plane. Populate
the SW node plane with vias, mainly around the exposed pad of
the inductor terminal and around the perimeter of the source of
Q1/Q2 and the drain of Q3/Q4. The output voltage power plane
(VOUT) is at the rightmost end of the evaluation board. This plane
should be replicated, descending down to multiple layers with
vias surrounding the inductor terminal and the positive terminals
of the output bulk capacitors. Ensure that the negative terminals of
the output capacitors are placed close to the main power ground
(PGND), as previously mentioned. All of these points form a
tight circle (component geometry permitting) that minimizes
the area of flux change as the event switches between D and 1 D.
IC SECTION (LEFT SIDE OF EVALUATION BOARD)
A dedicated plane for the analog ground plane (GND) should
be separate from the main power ground plane (PGND). With
the shortest path possible, connect the analog ground plane to
the GND pin (Pin 5). This plane should be on only the top layer
of the evaluation board. To avoid crosstalk interference, there
should not be any other voltage or current pathway directly below
this plane on Layer 2, Layer 3, or Layer 4. Connect the negative
terminals of all sensitive analog components to the analog ground
plane. Examples of such sensitive analog components include
the resistor divider’s bottom resistor, the high frequency bypass
capacitor for biasing (0.1 μF), and the compensation network.
Mount a 1 μF bypass capacitor directly across the VREG pin
(Pin 7) and the PGND pin (Pin 13). In addition, a 0.1 μF should
be tied across the VREG pin (Pin 7) and the GND pin (Pin 5).
POWER SECTION
As shown in Figure 91, an appropriate configuration to localize
large current transfer from the high voltage input (VIN) to the
output (VOUT) and then back to the power ground is to put the
VIN plane on the left, the output plane on the right, and the main
power ground plane in between the two. Current transfers from
the input capacitors to the output capacitors, through Q1/Q2,
during the on state (see Figure 95). The direction of this current
(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns
on. When Q3/Q4 turns on, the current direction continues to be
maintained (yellow arrow) as it circles from the bulk capacitor
power ground terminal to the output capacitors, through
Q3/Q4. Arranging the power planes in this manner minimizes
the area in which changes in flux occur if the current through
Q1/Q2 stops abruptly. Sudden changes in flux, usually at the
source terminals of Q1/Q2 and the drain terminal of Q3/Q4,
cause large dv/dt at the SW node.
09
34
7-
0
86
Figure 95. Primary Current Pathways During the On State of the Upper-Side
MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADP2121ACBZ-1.85R7 | 1.222 A SWITCHING REGULATOR, 6640 kHz SWITCHING FREQ-MAX, PBGA6 |
| ADS-119MC | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP24 |
| ADS6243IRGZT | 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC48 |
| ADS6242IRGZTG4 | 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC48 |
| ADS7806PB | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDIP28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADP1875ARQZ-1.0-R7 | 功能描述:IC REG CTRLR BUCK PWM CM 16-QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:96% 電源電壓:4 V ~ 36 V 降壓:無 升壓:是 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:24-WQFN 裸露焊盤 包裝:帶卷 (TR) |
| ADP1876 | 制造商:AD 制造商全稱:Analog Devices 功能描述:600 kHz Dual Output Synchronous Buck |
| ADP1876ACPZ-R7 | 功能描述:IC REG CTRLR BUCK PWM CM 32LFCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 特色產(chǎn)品:LM3753/54 Scalable 2-Phase Synchronous Buck Controllers 標(biāo)準(zhǔn)包裝:1 系列:PowerWise® PWM 型:電壓模式 輸出數(shù):1 頻率 - 最大:1MHz 占空比:81% 電源電壓:4.5 V ~ 18 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-5°C ~ 125°C 封裝/外殼:32-WFQFN 裸露焊盤 包裝:Digi-Reel® 產(chǎn)品目錄頁面:1303 (CN2011-ZH PDF) 其它名稱:LM3754SQDKR |
| ADP1876-EVALZ | 功能描述:BOARD EVAL FOR ADP1876 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - DC/DC 與 AC/DC（離線）SMPS 系列:* 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:DC/DC，步降 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:3.3V 電流 - 輸出:3A 輸入電壓:4.5 V ~ 28 V 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):降壓 頻率 - 開關(guān):250kHz 板類型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名稱:497-12113STEVAL-ISA094V1-ND |
| ADP1877 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Output Synchronous Buck PWM Controller With Tracking |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。