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參數(shù)資料
| 型號(hào)： | ADP1875ARQZ-0.3-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 300 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | ROHS COMPLIANT, MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 25/44頁 |
| 文件大?。?/td> | 2475K |
| 代理商： | ADP1875ARQZ-0.3-R7 |
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ADP1874/ADP1875
Rev. 0 | Page 31 of 44
THERMAL CONSIDERATIONS
The ADP1874/ADP1875 are used for dc-to-dc, step down, high
current applications that have an on-board controller, an on-board
LDO, and on-board MOSFET drivers. Because applications may
require up to 20 A of load current and be subjected to high ambient
temperature, the selection of external upper- and lower-side
MOSFETs must be associated with careful thermal consideration
to not exceed the maximum allowable junction temperature of
125°C. To avoid permanent or irreparable damage, if the junction
temperature reaches or exceeds 155°C, the part enters thermal
shutdown, turning off both external MOSFETs and is not re-
enabled until the junction temperature cools to 140°C (see the
On-Board Low Dropout Regulator section).
In addition, it is important to consider the thermal impedance
of the package. Because the ADP1874/ADP1875 employ an
on-board LDO, the ac current (fxCxV) consumed by the internal
drivers to drive the external MOSFETs, adds another element of
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO.
Table 9 lists the thermal impedance for the ADP1874/ADP1875,
which are available in a 16-lead QSOP.
Table 9. Thermal Impedance for 16-lead QSOP
Parameter
Thermal Impedance
16-Lead QSOP θJA
4-Layer Board
104°C/W
Figure 89 specifies the maximum allowable ambient temperature
that can surround the ADP1874/ADP1875 IC for a specified
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 16-lead QSOP
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.
150
30
40
50
60
70
80
90
100
110
120
130
140
5.5
19.0
17.5
16.0
14.5
13.0
11.5
10.0
8.5
7.0
M
AX
IM
UM
A
L
O
W
ABL
E
AM
BI
E
NT
T
E
M
P
E
RAT
URE
(
°C)
VIN (V)
VOUT = 0.8V
VOUT = 1.8V
VOUT = HIGH SETPOINT
600kHz
300kHz
1MHz
09
34
7-
18
3
Figure 89. Ambient Temperature vs. VIN,
4-Layer EVB, CIN = 4.3 nF (Upper-/Lower-Side MOSFET)
The maximum junction temperature allowed for the ADP1874/
ADP1875 ICs is 125°C. This means that the sum of the ambient
temperature (TA) and the rise in package temperature (TR), which is
caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by the
following expression:
TJ = TR × TA
(1)
where:
TJ is the maximum junction temperature.
TR is the rise in package temperature due to the power
dissipated from within.
TA is the ambient temperature.
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
TR = θJA × PDR(LOSS)
(2)
where:
θJA is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
PDR(LOSS) is the overall power dissipated by the IC.
The bulk of the power dissipated is due to the gate capacitance of
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
internal low dropout regulator (see the MOSFET Driver Loss
section and the Efficiency Consideration section) are
PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] +
[VREG × (fSWClowerFET VREG + IBIAS)]
(3)
where:
CupperFET is the input gate capacitance of the upper-side MOSFET.
ClowerFET is the input gate capacitance of the lower-side MOSFET.
IBIAS is the dc current (2 mA) flowing into the upper- and lower-
side drivers.
VDR is the driver bias voltage (the low input voltage (VREG) minus
the rectifier drop (see Figure 87)).
VREG is the LDO output/bias voltage.
)
(
)
(
)
(
)
(
BIAS
TOTAL
SW
IN
LOSS
DR
LDO
DISS
I
VREG
C
f
VREG
V
P
+
×
+
=
(4)
where:
PDISS(LDO) is the power dissipated through the pass device in the
LDO block across VIN and VREG.
PDR(LOSS) is the MOSFET driver loss.
VIN is the high voltage input.
VREG is the LDO output voltage and bias voltage.
CTOTAL is the CGD + CGS of the external MOSFET.
IBIAS is the dc input bias current.
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