1. CL
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ADN4697EBRZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 5/20闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC RCVR LVDS 2CH 14SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 56
绯诲垪锛� *
Data Sheet
ADN4696E/ADN4697E
Rev. 0 | Page 13 of 20
RECEIVER MEASUREMENTS
A
NOTES
1. CL IS 20%, CERAMIC, SURFACE MOUNT, AND
PROBE/STRAY CAPACITANCE < 2cm FROM D.U.T.
VOUT
CL
15pF
B
10355-
030
RO
RE
VID
Figure 30. Receiver Timing Measurement
A
1.4V
1.0V
1.2V
RE INPUT
NOTES
1. CL IS 20% AND INCLUDES PROBE/STRAY
CAPACITANCE < 2cm FROM D.U.T.
2. RL IS 1% METAL FILM, SURFACE MOUNT, < 2cm FROM D.U.T.
VOUT
CL
15pF
RL
499
B
10355-
031
RO
RE
VTEST
Figure 31. Receiver Enable/Disable Time
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
100MHz; 50 卤1% DUTY CYCLE.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
VOH
VOL
0V
1/f0
INPUT
(VA 鈥� VB)
10355-
032
0.5VCC
1/f0
OUTPUT
(IDEAL)
VOH
VOL
OUTPUT
(ACTUAL)
tc(n)
tJ(PER) = |tc(n) 鈥� 1f0|
Figure 32. Receiver Period Jitter Characteristics
NOTES
1. INPUT PULSE GENERATOR: 50MHz; 50 卤5% DUTY CYCLE; tR, tF 鈮� 1ns.
2. MEASURED ON TEST EQUIPMENT WITH 鈥�3dB BANDWIDTH 鈮� 1GHz.
3. TYPE 2 RECEIVER: |VID| = 0.4V
tRPHL
VA
0.5VCC
VB
VOH
VOL
VID
VOUT
0.2V
鈥�0.2V
0V
90%
10%
90%
10%
0V
1.0V
1.2V
tF
tRPLH
tR
10355-
033
Figure 33. Receiver Propagation and Rise/Fall Times
0.5VCC
VCC
0V
VCC
0V
VOL
VOH
0.5VCC
VOH 鈥� 0.5V
RE INPUT
(VTEST = VCC)
(A = 1V)
VOUT
(VTEST = 0V)
(A = 1.4V)
10355-
034
tRPZH
tRPZL
VOL + 0.5V
tRPHZ
tRPLZ
NOTES
1. INPUT PULSE GENERATOR: 500kHz; 50 卤5% DUT Y CYCLE;
tR, tF 鈮� 1ns.
Figure 34. Receiver Enable/Disable Times
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
200Mbps; 215鈥�1PRBS.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
VOH
VOL
VA
VB
OUTPUT
INPUT
(PRBS)
tJ(PP)
0.5VCC
10355-
035
Figure 35. Receiver Peak-to-Peak Jitter Characteristics
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