參數(shù)資料
型號: ADN8102ACPZ-R7
廠商: Analog Devices Inc
文件頁數(shù): 1/36頁
文件大?。?/td> 0K
描述: IC EQUALIZER 4CH XSTREAM 64LFCSP
標準包裝: 750
系列: XStream™
應(yīng)用: 以太網(wǎng)控制器
接口: I²C
電源電壓: 1.8 V ~ 3.3 V
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
3.75 Gbps Quad Bidirectional
CX4 Equalizer
ADN8102
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2008–2010 Analog Devices, Inc. All rights reserved.
FEATURES
Optimized for dc to 3.75 Gbps data
Programmable input equalization
Up to 22 dB boost at 1.875 GHz
Compensates up to 30 meters of CX4 cable up to 3.75 Gbps
Compensates up to 40 inches of FR4 up to 3.75 Gbps
Programmable output pre-emphasis/de-emphasis
Up to 12 dB boost at 1.875 GHz (3.75 Gbps)
Compensates up to 15 meters of CX4 cable up to 3.75 Gbps
Compensates up to 40 inches of FR4 up to 3.75 Gbps
Flexible 1.8 V to 3.3 V core supply
Per lane P/N pair inversion for routing ease
Low power: 125 mW/channel up to 3.75 Gbps
DC- or ac-coupled differential CML inputs
Programmable CML output levels
50 Ω on-chip termination
Loss-of-signal detection
Temperature range operation: 40°C to +85°C
Supports 8b10b, scrambled, or uncoded NRZ data
I2C control interface
64-lead LFC
SP (QFN) package
APPLICATIONS
10GBase-CX4
HiGig
InfiniBand
1×, 2× Fibre Channel
XAUI
Gigabit Ethernet over backplane or cable
CPRI
50 Ω cables
FUNCTIONAL BLOCK DIAGRAM
RECEIVE
EQUALIZATION
EQ
TRANSMIT
PRE-EMPHASIS
PE
TRANSMIT
PRE-EMPHASIS
RECEIVE
EQUALIZATION
PE
2:1
CONTROL LOGIC
ADN8102
EQ
Ix_B[3:0]
LOS_B
LB
Ox_A[3:0]
ADDR[1:0]
SCL
SDA
RESET
Ox_B[3:0]
LOS_A
Ix_A[3:0]
PE_A[1:0]
EQ_A[1:0]
EQ_B[1:0]
PE_B[1:0]
ENA
ENB
0
7060-
001
Figure 1.
GENERAL DESCRIPTION
The ADN8102 is a quad, bidirectional, CX4 cable/backplane
equalizer with eight differential PECL-/CML-compatible inputs
with programmable equalization and eight differential CML
outputs with programmable output levels and pre-emphasis or
de-emphasis. The operation of this device is optimized for NRZ
data at rates up to 3.75 Gbps.
The receive inputs provide programmable equalization to
compensate for up to 30 meters of CX4 cable (24 AWG) or
40 inches of FR4, and programmable pre-emphasis to compensate
for up to 15 meters of CX4 cable (24 AWG) or 40 inches of FR4
at 3.75 Gbps. Each channel also provides programmable loss-of-
signal detection and loopback capability for system testing and
debugging.
The ADN8102 is controlled through toggle pins, an I2C control
interface that provides more flexible control, or a combination of
both. Every channel implements an asynchronous path supporting
dc to 3.75 Gbps NRZ data, fully independent of other channels. The
ADN8102 has low latency and very low channel-to-channel skew.
The main application for the ADN8102 is to support switching
in chassis-to-chassis applications over CX4 or InfiniBand cables.
The ADN8102 is packaged in a 9 mm × 9 mm 64-lead LFCSP
(QFN) package and operates from 40°C to +85°C.
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