VCC = 3 V to 3.6 V; R
參數(shù)資料
型號: ADN4661BRZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 7/12頁
文件大?。?/td> 0K
描述: IC DRIVER DIFF LVDS 1CH 8SOIC
標(biāo)準(zhǔn)包裝: 1,000
類型: 驅(qū)動器
驅(qū)動器/接收器數(shù): 1/0
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 帶卷 (TR)
ADN4661
Rev. 0 | Page 4 of 12
AC CHARACTERISTICS
VCC = 3 V to 3.6 V; RL = 100 Ω; CL1 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
Symbol
Min
Typ
Max
Unit
Conditions/Comments3, 4
Differential Propagation Delay High to Low
tPHLD
0.3
0.8
1.5
ns
Differential Propagation Delay Low to High
tPLHD
0.3
1.1
1.5
ns
Differential Pulse Skew |tPHLD tPLHD|5
tSKD1
0
0.3
0.7
ns
Differential Part-to-Part Skew6
tSKD3
0
1.0
ns
Differential Part-to-Part Skew7
tSKD4
0
1.2
Ns
Rise Time
tTLH
0.2
0.5
1.0
ns
Fall Time
tTHL
0.2
0.5
1.0
ns
Maximum Operating Frequency8
fMAX
350
MHz
1 CL includes probe and jig capacitance.
2 AC parameters are guaranteed by design and characterization.
3 Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tTLH ≤ 1 ns, and tTHL ≤ 1 ns.
4 All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
5 tSKD1 = |tPHLD tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
6 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
7 tSKD4, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum minimum| differential propagation delay.
8 fMAX generator input conditions: tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels
switching.
Test Circuits and Timing Diagrams
07
87
6-
0
02
RL/2
DIN
DOUT+
DOUT–
VCC
VOS
VOD
V
Figure 2. Test Circuit for Driver VOD and VOS
07
87
6-
0
03
CL
DIN
DOUT+
DOUT–
NOTES
1. CL INCLUDES PROBE AND JIG CAPACITANCE.
SIGNAL
GENERATOR
VCC
50
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
0
787
6-
0
04
DIN
VDIFF
tPLHD
tPHLD
VDIFF = DOUT+ –DOUT–
VOH
VOL
VOD
3V
1.5V
0V (DIFFERENTIAL)
0V
80%
20%
0V
DOUT+
DOUT–
tTLH
tTHL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
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