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參數(shù)資料
| 型號： | ADN2820S21 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
| 中文描述： | 10.7 Gbps的，3.3，低噪聲，與平均功率監(jiān)視器行業(yè)協(xié)會 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 786K |
| 代理商： | ADN2820S21 |
ADN2820
PAD LAYOUT AND FUNCTIONAL DESCRIPTIONS
PAD LAYOUT
Rev. 0 | Page 5 of 12
DIE INFORMATION
Die Size
0.875 mm × 1.060 mm
Die Thickness
12 mils = 0.3 mm
Passivation Openings
0.08 mm × 0.08 mm
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
VCC
VCC
GND
GND
GND
GND
OUT
OUTB
TEST
IN
OFFSET
CLF
POWMON
0,0'
03194-0-002
Figure 2. ADN2820 Pad Layout
0.12 mm × 0.08 mm
0.08 mm × 0.12 mm
Passivation Composition
5000 Si
3
N
4
(Top)
+5000 SiO
2
(Bottom)
Pad Composition
Al/1% Cu
Backside Contact
P-Type Handle (Oxide Isolated from Active Circuitry)
PAD DESCRIPTIONS
Table 3. Pad Descriptions
Pin No.
1–3
4, 7, 10, 11
5
6
8
Pad
VCC
GND
OUT
OUTB
POWMON
Function
Positive Supply. Bypass to GND with a 100 pF or greater single-layer capacitor.
Ground.
Positive Output. Drives 50 termination (ac or dc termination).
Negative Output. Drives 50 termination (ac or dc termination).
Input Average Power Monitor. Analog signal proportional to average optical input power. Leave open if
unused.
Low Frequency Cutoff Setpoint. Connect with a 0.1 μF capacitor to GND for 20 kHz.
Test Pad. Leave Floating.
Current Input. Bond directly to reverse biased PIN or APD anode. Filter PIN or APD anode with 100 pF × 100
or greater.
Output Offset Adjust Input. Leave open if not being used and the input slice threshold will automatically be set
to the eye center.
9
12
13
CLF
TEST
IN
14
OFFSET
PAD COORDINATES
Table 4. Pad Coordinates
Pin
No.
PAD
1
VCC
2
VCC
3
VCC
4
GND
5
OUT
6
OUTB
7
GND
X (mm)
–0.20
0.00
0.20
0.35
0.35
0.35
0.35
Y (mm)
0.45
0.45
0.45
0.30
0.10
–0.10
–0.30
Pin
No.
8
9
10
11
12
13
14
PAD
POWMON
CLF
GND
GND
TEST
IN
OFFSET
X (mm)
0.20
0.00
–0.20
–0.35
–0.35
–0.35
–0.35
Y (mm)
–0.45
–0.45
–0.45
–0.30
–0.10
0.10
0.30
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