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參數(shù)資料
| 型號： | ADN2819ACPZ-CML-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 48LFCSP |
| 標準包裝： | 2,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 帶卷 (TR) |
ADN2819
Rev. B | Page 15 of 24
100k
100k
BUFFER
ADN2819
VCC/2
REFCLKN
REFCLKP
CRYSTAL
OSCILLATOR
XO1
XO2
REFSEL
NC
19.44MHz
VCC
02999-B
-019
Figure 19. Crystal Oscillator Configuration
The ADN2819 can accept any of the following reference clock
frequencies: 19.44 MHz, 38.88 MHz, and 77.76 MHz at LVTTL/
LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/
LVDS levels via the REFCLKN/P inputs, independent of data
rate (including Gigabit Ethernet and wrapper rates). The input
buffer accepts any differential signal with a peak-to-peak
differential amplitude of greater than 100 mV (e.g., LVPECL or
LVDS) or a standard single-ended low voltage TTL input,
providing maximum system flexibility. The appropriate division
ratio can be selected using the REFSEL0/1 pins, according to
Table 6. Phase noise and duty cycle of the reference clock are
not critical, and 100 ppm accuracy is sufficient.
Table 6. Reference Frequency Selection
REFSEL
REFSEL[1..0]
Applied Reference Frequency
(MHz)
1
00
19.44
1
01
38.88
1
10
77.76
1
11
155.52
0
XX
REFCLKP/N Inactive. Use 19.44 MHz
XTAL on Pins XO1, XO2 (pull REFCLKP
to VCC)
An on-chip oscillator to be used with an external crystal is also
provided as an alternative to using the REFCLKN/P inputs.
Details of the recommended crystal are given in Table 7.
Table 7. Required Crystal Specifications
Parameter
Value
Mode
Series Resonant
Frequency/Overall Stability
19.44 MHz ± 100 ppm
Frequency Accuracy
±100 ppm
Temperature Stability
±100 ppm
Aging
±100 ppm
ESR
50 max
REFSEL must be tied to VCC when the REFCLKN/P inputs are
active, or tied to VEE when the oscillator is used. No connection
between the XO pin and the REFCLK input is necessary (see
Figure 17, Figure 18, and Figure 19). Note that the crystal should
operate in series resonant mode, which renders it insensitive to
external parasitics. No trimming capacitors are required.
LOCK DETECTOR OPERATION
The lock detector monitors the frequency difference between
the VCO and the reference clock, and deasserts the loss of lock
signal when the VCO is within 500 ppm of center frequency.
This enables the phase loop, which then maintains phase lock,
unless the frequency error exceeds 0.1%. Should this occur, the
loss of lock signal is reasserted and control returns to the fre-
quency loop, which will reacquire and maintain a stable clock
signal at the output. The frequency loop requires a single exter-
nal capacitor between CF1 and CF2. The capacitor specification
is given in Table 8.
Table 8. Recommended CF Capacitor Specification
Parameter
Value
Temperature Range
–40°C to +85°C
Capacitance
>3.0 F
Leakage
<80 nA
Rating
>6.3 V
1000
500
0
500
1000
fVCO ERROR
(ppm)
LOL
1
02999-B
-020
Figure 20. Transfer Function LOL
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