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參數(shù)資料
| 型號： | ADN2819ACPZ-CML-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 帶卷 (TR) |
ADN2819
Rev. B | Page 19 of 24
CHOOSING AC-COUPLING CAPACITORS
The choice of ac-coupling capacitors at the input (PIN, NIN)
and output (DATAOUTP, DATAOUTN) of the ADN2819 must
be chosen such that the device works properly at the lower
OC-3 and higher OC-48 data rates. When choosing the
capacitors, the time constant formed with the two 50 resistors
in the signal path must be considered. When a large number of
consecutive identical digits (CIDs) are applied, the capacitor
voltage can drop due to baseline wander (see Figure 23), causing
pattern dependent jitter (PDJ).
For the ADN2819 to work robustly at both OC-3 and OC-48, a
minimum capacitor of 1.6 F to PIN/NIN and 0.1 F on
DATAOUTP/DATAOUTN should be used. This is based on the
assumption that 1000 CIDs must be tolerated and that the PDJ
should be limited to 0.01 UI p-p.
50
ADN2819
NIN
PIN
50
VREF
CIN
V2
V1
V2b
V1b
TIA
LIMAMP
CDR
COUT
DATAOUTP
DATAOUTN
+
4
3
2
1
V1
V1b
V2
V2b
VDIFF
VDIFF = V2–V2b
VTH = ADN2819 QUANTIZER THRESHOLD
VREF
VTH
NOTES
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF LEVEL,
WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS,
CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON
THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2819. THE QUANTIZER WILL BE
ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
02999-B
-025
Figure 25. Example of Baseline Wander
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| ADN2819ACPZ-CML-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2820 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
| ADN2820ACHIPS | 制造商:Analog Devices 功能描述: |
| ADN2820S21 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10.7 Gbps, 3.3V, Low Noise, TIA with Average Power Moniter |
| ADN2821 | 制造商:AD 制造商全稱:Analog Devices 功能描述:11.1 Gbps 3.3V Transimpedance Amplifier |
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