參數(shù)資料
型號(hào)： ADM1041AARQZ-REEL
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Secondary-Side Controller with Current Share and Housekeeping
中文描述： SPECIALTY TELECOM CIRCUIT, PDSO24
封裝： LEAD FREE, MO-137AE, QSOP-24
文件頁(yè)數(shù)： 47/56頁(yè)
文件大?。?/td> 991K
代理商： ADM1041AARQZ-REEL
ADM1041A
Table 36. Register 1Bh, Sel CBD/SMBAlert2. Power-On Default from EEPROM Register 811Bh During Power-Up
Bit No.
Name
R/W
Description
This register allows the user to set the CBD/Alert pin when certain flag conditions occur. These
bits are set up in an OR function so that any one flag can set the CBD/Alert pin. This register is
used with Register 1Ah.
7
selcbd2 <7>
R/W
V
DD
OK b (inverted)
6
selcbd2 <6>
R/W
MON 1 flag
5
selcbd2 <5>
R/W
MON 2 flag
4
selcbd2 <4>
R/W
MON 3 flag
3
selcbd2 <3>
R/W
MON 4 flag
2
selcbd2 <2>
R/W
Micro CBD write. Microprocessor control of CBD
1
selcbd2 <1>
R/W
Mon5 flag
0
selcbd2 <0>
R/W
Not used.
Rev. 0 | Page 47 of 56
Table 37. Register 1Ch, Manufacturer’s ID. Power-On Default 41h.
Bit No.
Name
R/W
7–0
Manufacturer’s ID
Code
Description
This register contains the manufacturer’s ID code for the device. It is used by the manufacturer
for test purposes and should not be read from or written to in normal operation.
R
Table 38. Register 1Dh, Revision Register. Power-On Default 01h.
Bit No.
Name
7–4
Major Revision Code
3–0
Minor Revision Code
R/W
R
R
Description
These 4 bits denote the generation of the device.
These 4 bits contain the manufacturer’s code for minor revisions to the device: Rev 0 = 0h,
Rev 1 = 1h, and so on.
This register is used by the manufacturer for test purposes. It should not be read from or
written to in normal operation.
Table 39. Register 2Ah, Status1 Mirror Latched. Power-On Default 00h.
These flags are cleared by a register read, provided the fault no longer persists. See also Table 43. Note that latched bits are clocked on a
low-to-high transmission only. Also note that these register bits are cleared when read via the SMBus, except if the fault is still present. It
is recommended to read the register again after the faults disappear to ensure reset.
Bit No.
7
6
5
4
3
2
1
0
Name
OV Fault Latch
UV Fault Latch
OCP Timeout Latch
Mon1 Flag Latch
Mon2 Flag Latch
Mon3 Flag Latch
Mon4 Flag Latch
Mon5 Flag Latch
R/W
R
R
R
R
R
R
R
R
Description
Overvoltage fault has occurred.
Undervoltage fault has occurred.
Overcurrent has occured and timed out (ocpf is in Status3 register).
MON1 flag.
MON2 flag.
MON3 flag.
MON4 flag.
MON5 flag.
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