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參數(shù)資料
| 型號(hào)： | ADM1041AARQZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Secondary-Side Controller with Current Share and Housekeeping |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO24 |
| 封裝： | LEAD FREE, MO-137AE, QSOP-24 |
| 文件頁數(shù)： | 40/56頁 |
| 文件大?。?/td> | 991K |
| 代理商： | ADM1041AARQZ-REEL |
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ADM1041A
Bit No.
1–0
Rev. 0 | Page 40 of 56
Name
Load OV Recover
R/W
R/W
Description
b1
0
0
1
1
b0
0
1
0
1
Function
Add 100 μs delay
Add 200 μs delay
Add 300 μs delay
Add 400 μs delay
Table 13. Register 04h, Current-Sense CC. Power-On Default from EEPROM Register 8104h During Power-Up
Bit No.
Name
R/W
Description
7–3
Current-Limit Trim
R/W
This register contains the current-sense trim level setting at which current limiting starts. Five
bits. Setting all bits to 1 results in maximum current limit (130%).
2
Reserved
R/W
Don’t Care. This should be set to “0” for normal operation.
1–0
Share OK Threshold
R/W
b1
b0
0
0
0
1
1
0
1
1
Table 14. Register 05h, Current Share Offset. Power-On Default from EEPROM Register 8105h During Power-Up
Bit No.
Name
R/W
Description
7–0
Current Share Offset
R/W
This register contains the current-share offset trim level. Writing 00h corresponds to the
minimum offset. FFh corresponds to maximum offset. See the Current Limit Error Amplifier
section in the Table 1 for more information.
Table 15. Register 06h, Current Share Slope. Power-On Default from EEPROM Register 8106h During Power-Up
Bit No.
Name
R/W
Description
7–1
Current Share Slope
R/W
This register contains current share slope trim level. Increasing this results in a steeper slope
for the current share. This register is normally written to during the user calibration. It is used
with Reg15h for trimming the current share.
0
Reserved
R/W
Don’t Care.
Table 16. Register 07h, EEPROM_lock. Power-On Default from EEPROM Register 8107h During Power-Up
Bit No.
Name
R/W
Description
7
Reserved
R/W
Don’t Care
6
Lock6
R/W
Locks 8140h–817Fh
5
Lock5
R/W
Locks 8120h–813Fh
4
Lock4
R/W
Locks 8100h–811Fh
3
Lock3
R/W
Locks 80C0h–80FFh
2
Lock2
R/W
Locks 8080h–80BFh
1
Lock1
R/W
Locks 8040h–807Fh
0
Lock0
R/W
Locks 8000h–803Fh
Function
±100 mV
±200 mV
±300 mV
±400 mV
Available FRU.
ADI cal registers, locked by manufacturer.
ADM1041A configuration boot registers.
Available FRU.
Available FRU.
Available FRU.
Available FRU.
Table 17. Register 08h, Load OV Fine. Power-On Default from EEPROM Register 8108h During Power-Up
Bit No.
Name
R/W
Description
7–0
Load OV Trim
R/W
Load OV Trim. This range is programmable from 105% to 120% of the nominal load voltage. 00h
corresponds to 105%. Each LSB results in an increase of 1.6 mV.
Table 18. Register 09h, Local UVP Trim. Power-On Default from EEPROM Register 8109h During Power-Up
Bit No.
Name
R/W
Description
7–0
local_uvp
R/W
This register contains the local undervoltage settings. This can be programmed from 1.3 V to
2.1 V when the nominal voltage is 2 V. Each LSB increases the UV clamp setting by 3.1 mV. See
the Local Overvoltage specifications in Table 1.
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| ADM1041ARQ-2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADM1041ARQ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Secondary-Side Controller with Current Share and Housekeeping |
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