參數(shù)資料
型號： ADM1030ARQ-REEL7
廠商： ANALOG DEVICES INC
元件分類： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 1Cel, RECTANGULAR, SURFACE MOUNT
封裝： MO-137AB, QSOP-16
文件頁數(shù)： 12/28頁
文件大?。?/td> 495K
代理商： ADM1030ARQ-REEL7
REV. A
–2–
ADM1030–SPECIFICATIONS1 (T
A = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Voltage, VCC
3.0
3.30
5.5
V
Supply Current, ICC
1.4
3
mA
Interface Inactive, ADC Active
32
50
mA
Standby Mode
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy
±1
±3
∞C
Resolution
0.25
∞C
External Diode Sensor Accuracy
±1
∞C60∞C TD 100∞C
Resolution
0.125
∞C
Remote Sensor Source Current
180
mA
High Level
11
mA
Low Level
OPEN-DRAIN DIGITAL OUTPUTS
(
THERM, INT, FAN_FAULT, PWM_OUT)
Output Low Voltage, VOL
0.4
V
IOUT = –6.0 mA; VCC = 3 V
High-Level Output Leakage Current, IOH
0.1
1
mAVOUT = VCC; VCC = 3 V
DIGITAL INPUT LEAKAGE CURRENT
Input High Current, IIH
–1
mAVIN = VCC
Input Low Current, IIL
1
mAVIN = 0
Input Capacitance, CIN
5pF
DIGITAL INPUT LOGIC LEVELS
2
(ADD,
THERM, TACH)
Input High Voltage, VIH
2.1
V
Input Low Voltage, VIL
0.8
V
OPEN-DRAIN SERIAL DATA
BUS OUTPUT (SDA)
Output Low Voltage, VOL
0.4
V
IOUT = –6.0 mA; VCC = 3 V
High-Level Output Leakage Current, IOH
0.1
1
mAVOUT = VCC
SERIAL BUS DIGITAL INPUTS
(SCL, SDA)
Input High Voltage, VIH
2.1
V
Input Low Voltage, VIL
0.8
V
Hysteresis
500
mV
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
±6%
60
∞C TA 100∞C
Resolution
8
Bits
TACH Nominal Input RPM
4400
RPM
Divisor N = 1, Fan Count = 153
2200
RPM
Divisor N = 2, Fan Count = 153
1100
RPM
Divisor N = 4, Fan Count = 153
550
RPM
Divisor N = 8, Fan Count = 153
Conversion Cycle Time
637
ms
SERIAL BUS TIMING
3
Clock Frequency, fSCLK
10
100
kHz
See Figure 1
Glitch Immunity, tSW
50
ns
See Figure 1
Bus Free Time, tBUF
4.7
ms
See Figure 1
Start Setup Time, tSU;STA
4.7
ms
See Figure 1
Start Hold Time, tHD;STA
4
ms
See Figure 1
Stop Condition Setup Time tSU;STO
4
ms
See Figure 1
SCL Low Time, tLOW
1.3
ms
See Figure 1
SCL High Time, tHIGH
450
ms
See Figure 1
SCL, SDA Rise Time, tR
1000
ns
See Figure 1
SCL, SDA Fall Time, tF
300
ns
See Figure 1
Data Setup Time, tSU;DAT
250
ns
See Figure 1
Data Hold Time, tHD;DAT
300
ns
See Figure 1
NOTES
1Typicals are at T
A = 25
∞C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.
2ADD is a three-state input that may be pulled high, low or left open-circuit.
3Timing specifications are tested at logic levels of V
IL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.
Specifications subject to change without notice.
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