參數(shù)資料
型號(hào)： ADM1030ARQ-REEL7
廠商： ANALOG DEVICES INC
元件分類： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 1Cel, RECTANGULAR, SURFACE MOUNT
封裝： MO-137AB, QSOP-16
文件頁(yè)數(shù)： 10/28頁(yè)
文件大?。?/td> 495K
代理商： ADM1030ARQ-REEL7
REV. A
ADM1030
–18–
Effect of ADC Sample Rate on Filtered Mode
The second means by which to change the Filtered Mode char-
acteristics is to adjust the ADC sample rate. The faster the ADC
sample rate, the more temperature samples are obtained per
second. One way to apply filtering to the control loop is to
slow down the ADC sampling rate. This means that the num-
ber of iterations of the Filtered Mode algorithm per second
are effectively reduced. If the number of temperature measure-
ments per second are reduced, how often the PWM_OUT
signal controlling the fan is updated is also reduced.
Bits <4:2> of the Fan Filter Register (Reg 0x23) set the ADC
sample rate. The default ADC sample rate is 1.4 kHz. The
ADC sample rate is selectable from 87.5 Hz to 11.2 kHz.
Table IX shows how many temperature samples are obtained
per second, for each of the ADC sample rates.
Table IX. Temperature Updates per Second
ADC Sample Rate
Temperature Updates/Sec
87.5 Hz
0.0625
175 Hz
0.125
350 Hz
0.25
700 Hz
0.5
1.4 kHz
1 (Default)
2.8 kHz
2
5.6 kHz
4
11.2 kHz
8
RELEVANT REGISTERS FOR FILTERED AUTOMATIC
FAN SPEED CONTROL MODE
In addition to the registers used to program the normal Auto-
matic Fan Speed Control Mode, the following register needs to
be programmed.
Register 0x23 Fan Filter Register
<7>
Spin-up Disable :- when this bit is set to 1, fan spin-up
is disabled. (Default = 0)
<6:5> Ramp Rate: these bits set the ramp rate for filtered mode.
00 = 1 (0.416% Duty Cycle Change)
01 = 2 (0.833% Duty Cycle Change)
10 = 4 (1.66% Duty Cycle Change)
11 = 8 (3.33% Duty Cycle Change)
<4:2> ADC Sample Rate
000 = 87.5 Hz
001 = 175 Hz
010 = 350 Hz
011 = 700 Hz
100 = 1.4 kHz (Default)
101 = 2.8 kHz
110 = 5.6 kHz
111 = 11.2 kHz
<1>
Unused. Default = 0
<0>
Fan 1 Filter Enable: when this bit is set to 1, it enables
filtering on Fan 1. Default = 0.
PROGRAMMING THE FILTERED AUTOMATIC FAN
SPEED CONTROL LOOP
1. Program a value for TMIN.
2. Program a value for the slope TRANGE.
3. TMAX = TMIN + TRANGE.
4. Program a value for Fan Spin-up Time.
5. Program the desired Automatic Fan Speed Control Mode
Behavior, i.e., which temperature channel controls the fan.
6. Program a ramp rate for the filtered mode.
7. Program the ADC sample rate in the Fan Filter Register.
8. Set Bit 0 to enable fan filtered mode for the fan.
9. Select Automatic Fan Speed Control Mode by setting Bit 7 of
Configuration Register 1.
PWM DUTY CYCLE SELECT MODE
The ADM1030 may be operated under software control by clear-
ing Bit 7 of Configuration Register 1 (Register 0x00). This
allows the user to directly control PWM Duty Cycle.
Clearing Bit 5 of Configuration Register 1 allows fan control by
varying PWM duty cycle. Values of duty cycle between 0% to
100% may be written to the Fan Speed Config Register (0x22)
to control the speed of the fan. Table X shows the relationship
between hex values written to the Fan Speed Configuration
Register and PWM duty cycle obtained.
Table X. PWM Duty Cycle Select Mode
Hex Value
PWM Duty Cycle
00
0%
01
7%
02
14%
03
20%
04
27%
05
33%
06
40%
07
47%
08
53%
09
60%
0A
67%
0B
73%
0C
80%
0D
87%
0E
93%
0F
100%
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