參數(shù)資料
型號: ADL5565ACPZ-R7
廠商: Analog Devices Inc
文件頁數(shù): 13/28頁
文件大小: 0K
描述: IC AMP DIFF 6GHZ 16LFCSP
特色產(chǎn)品: RF ICs
標(biāo)準(zhǔn)包裝: 1
放大器類型: RF/IF 差分
電路數(shù): 1
轉(zhuǎn)換速率: 11000 V/µs
-3db帶寬: 7GHz
電流 - 輸入偏壓: 5µA
電流 - 電源: 80mA
電流 - 輸出 / 通道: 30mA
電壓 - 電源,單路/雙路(±): 2.8 V ~ 5.2 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-WQ(3x3)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ADL5565ACPZ-R7DKR
ADL5565
Data Sheet
ADC INTERFACING
The ADL5565 is a high output linearity amplifier that is optimized
for ADC interfacing. There are several options available to the
designer when using the ADL5565. Figure 40 uses a wideband
1:1 transmission line balun followed by two 40 resistors in
parallel with the three input impedances (which change with
the gain selection of the ADL5565) to provide a 50
differential impedance and provides a wideband match to a
50 source. The ADL5565 is ac-coupled from the AD9467 to
avoid common-mode dc loading. The 33 resistors improve the
isolation between the ADL5565 and any switching currents
present at the analog-to-digital, sample-and-hold circuitry. The
AD9467 input presents a 530 differential load impedance and
requires a 2 V to 2.5 V differential input swing to reach full scale
(VREF = 1 V to 1.25 V). This circuit provides variable gain,
isolation, and source matching for the AD9467.
Applying a full-scale, single-tone signal from the ADL5565, an
SFDR of 91.9 dBc is realized (see Figure 37). Applying two half-
scale signals from the ADL5565 in a gain of 6 dB, an SFDR of
86.4 dBc is achieved at 100 MHz (see Figure 38). The bandwidth
of the circuit in Figure 40 is shown in Figure 39.
0
15
0
30
45
60
75
90
105
120
GAIN = 6dB
SNR = 69.42dBc
SFDR = 91.9dBc
SECOND = –95.5dBc
THIRD = –96.5dBc
NOISE FLOOR = –115.6dB
A
MPL
IT
U
D
E
(d
B
F
S)
FREQUENCY (MHz)
–15
–30
–45
–60
–75
–90
–105
–120
–135
–150
09959-
049
Figure 37. Measured Single-Tone Performance of the
Circuit in Figure 40 for a 100 MHz Input Signal
2F2 – F1
2F1 – F2
F1 – F2
2F2 – F1
2F1 + F2
F1 + F2
0
15
0
30
45
60
75
90
105
120
FUNDAMENTAL1 = –7.034dBFS
FUNDAMENTAL2 = –7.053dBFS
IMD (2f1 – f2) = –90.677dBc
IMD (2f2 + f1) = –92.101dBc
NOISE FLOOR = –115.2dB
A
MPL
IT
U
D
E
(d
B
F
S)
FREQUENCY (MHz)
–15
–30
–45
–60
–75
–90
–105
–120
–135
–150
09959-
041
Figure 38. Measured Two-Tone Performance of the Circuit in Figure 40 for a
100 MHz and 102 MHz Input Signals
5
4
3
2
1
0
100
200
300
400
500
N
OR
M
A
LIZE
D
(
dB
FS
)
FREQUENCY (MHz)
09959-
042
Figure 39. Measured Frequency Response of the Wideband
ADC Interface Depicted in Figure 40
The wideband frequency response is an advantage in broad-
band applications, such as predistortion receiver designs and
instrumentation applications. However, by designing for a wide
analog input frequency range, the cascaded SNR performance is
somewhat degraded due to high frequency noise aliasing into
the wanted Nyquist zone.
0.1F
40
50
AC
0.1
F
ETC1-1-13
VIN1
VIP1
VIP2
A
B
VIN2
40
ADL5565
+
0.1F
0.1
F
33
VOP
VON
33
+
AD9467
16-BIT ADC
16
VIN+
VIN–
09959-
039
Figure 40. Wideband ADC Interfacing Example Featuring the AD9467
Rev. E | Page 20 of 28
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