參數(shù)資料
型號(hào): ADL5565ACPZ-R7
廠商: Analog Devices Inc
文件頁數(shù): 10/28頁
文件大小: 0K
描述: IC AMP DIFF 6GHZ 16LFCSP
特色產(chǎn)品: RF ICs
標(biāo)準(zhǔn)包裝: 1
放大器類型: RF/IF 差分
電路數(shù): 1
轉(zhuǎn)換速率: 11000 V/µs
-3db帶寬: 7GHz
電流 - 輸入偏壓: 5µA
電流 - 電源: 80mA
電流 - 輸出 / 通道: 30mA
電壓 - 電源,單路/雙路(±): 2.8 V ~ 5.2 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-WQ(3x3)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ADL5565ACPZ-R7DKR
ADL5565
Data Sheet
INPUT AND OUTPUT INTERFACING
The ADL5565 can be configured as a differential input to
differential output driver, as shown in Figure 32. The resistors,
R1 and R2, combined with the ETC1-1-13 balun transformer,
provide a 50 Ω input match for the three input impedances that
change with the variable gain strapping. The input and output
0.1 F capacitors isolate the VCC/2 bias from the source and
balanced load. The load should equal 200 to provide the
expected ac performance (see the Specifications section and the
3V TO 5V
VIP2
VIP1
VIN1
VIN2
A
B
50
AC
R2
+
0.1F
ETC1-1-13
0.1F
+
R1
+
0.1F
NOTES
1. FOR 6dB GAIN (AV = 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1.
2. FOR 12dB GAIN (AV = 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2.
3. FOR 15.5dB GAIN (AV = 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2
AND INPUT B TO BOTH VIN1 AND VIN2.
RL
2
RL
2
09959-
034
Figure 32. Differential Input to Differential Output Configuration
Table 6. Differential Termination Values for Figure 32
Gain (dB)
R1 ()
R2 ()
6
29
12
33
15.5
40.2
The differential gain of the ADL5565 is dependent on the
source impedance and load, as shown in Figure 33.
100
200
200
100
50
50
VIP2
VIP1
VIN1
VIN2
5
5
RL
AC
1/2 RS
0.1F
+
0.1F
+
09959-
035
Figure 33. Differential Input Loading Circuit
The differential gain can be determined using the following
formula. The values of RG for each gain configuration are shown
L
G
V
R
A
+
×
=
10
200
(1)
In Equation 1, RG is the gain setting resistor (see Figure 1).
Table 7. Values of RG for Differential Gain
Gain (dB)
RG ()
6
100
12
50
15.5
33.5
Single-Ended Input to Differential Output
The ADL5565 can also be configured in a single-ended input
to differential output driver, as shown in Figure 34. In this
configuration, the gain of the part is reduced due to the application
of the signal to only one side of the amplifier. The strappable
gain values are listed in Table 8 with the required terminations
to match to a 50 source using R1 and R2. The input and output
0.1 F capacitors isolate the VCC/2 bias from the source and the
balanced load. The performance for this configuration is shown
VIP2
VIP1
VIN1
VIN2
A
B
50
AC
R2
+
0.1F
3V TO 5V
+
R1
NOTES
1. FOR 5.3dB GAIN (AV = 1.84), CONNECT INPUT A TO VIP1
AND INPUT B TO VIN1.
2. FOR 10.3dB GAIN (AV = 3.3), CONNECT INPUT A TO VIP2
AND INPUT B TO VIN2.
3. FOR 13dB GAIN (AV = 4.5), CONNECT INPUT A TO BOTH
VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.
+
0.1F
RL
2
RL
2
09959-
036
Figure 34. Single-Ended Input to Differential Output Configuration
Table 8. Single-Ended Termination Values for Figure 34
Gain (dB)
R1 ()
R2 ()
5.3
30
73
10.3
30
104
13
30
154
The single-ended gain configuration of the ADL5565 is dependent
on the source impedance and load, as shown in Figure 35.
RL
200
200
VIP2
VIP1
VIN1
VIN2
5
5
RS
AC
R2
+
0.1F
+
R1
+
2
RL
2
100
100
50
50
09959-
037
Figure 35. Single-Ended Input Loading Circuit
Rev. E | Page 18 of 28
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