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參數(shù)資料
| 型號： | ADL5372ACPZ-R2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 調(diào)制器/解調(diào)器 |
| 英文描述： | 1500 MHz - 2500 MHz RF/MICROWAVE QUADRAPHASE MODULATOR |
| 封裝： | LEAD FREE, MO-220VGGD-2, LFCSP-24 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 802K |
| 代理商： | ADL5372ACPZ-R2 |
ADL5372
Rev. 0 | Page 12 of 24
BASIC CONNECTIONS
Figure 25 shows the basic connections for the ADL5372.
VPS5
VPS3
VPS4
VPS2
VOUT
CO
M
2
LO
IN
LOIP
CO
M
2
CO
M
3
CO
M
3
Q
BBP
CO
M
4
Q
BBN
CO
M
4
IBBN
IBBP
COM1
VPS1
COM1
VPS1
1
2
3
4
5
6
18
17
16
15
14
13
VOUT
C13
0.1F
C11
OPEN
C12
0.1F
CLON
100pF
C14
0.1F
C15
0.1F
C16
0.1F
24
23
22
21
20
19
7
8
9
10
11
12
COUT
100pF
VPOS
VP
O
S
QBBP
QBBN
IBBN
IBBP
EXPOSED PADDLE
CLOP
100pF
LO
GND
Z1
F-MOD
06
51
1-
0
25
Figure 25. Basic Connections for the ADL5372
Power Supply and Grounding
All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled
with a 0.1 μF capacitor. These capacitors should be located as
close as possible to the device. The power supply can range
between 4.75 V and 5.25 V.
The COM1 pin, COM2 pin, COM3 pin, and COM4 pin should
be tied to the same ground plane through low impedance paths.
The exposed paddle on the underside of the package should also
be soldered to a low thermal and electrical impedance ground
plane. If the ground plane spans multiple layers on the circuit
board, they should be stitched together with nine vias under the
exposed paddle. The Application Note AN-772 discusses the
thermal and electrical grounding of the LFCSP in detail.
Baseband Inputs
The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. The nominal drive level of
1.4 V p-p differential (700 mV p-p on each pin) should be
biased to a common-mode level of 500 mV dc.
The dc common-mode bias level for the baseband inputs may
range from 400 mV to 600 mV. This results in a reduction in
the usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5372 input range and on the top end by the output compliance
range on most DACs from Analog Devices.
LO Input
A single-ended LO signal should be applied to the LOIP pin
through an ac coupling capacitor. The recommended LO drive
power is 0 dBm. The LO return pin, LOIN, should be ac-coupled
to ground through a low impedance path.
The nominal LO drive of 0 dBm can be increased to up to 6 dBm
to realize an improvement in the noise performance of the
modulator. This improvement is tempered by degradation in
the sideband suppression performance (see Figure 20) and,
therefore, should be used judiciously. If the LO source cannot
provide the 0 dBm level, then operation at a reduced power
below 0 dBm is acceptable. Reduced LO drive results in slightly
increased modulator noise. The effect of LO power on sideband
suppression and carrier feedthrough is shown in Figure 20. The
effect of LO power on GSM noise is shown in Figure 35.
RF Output
The RF output is available at the VOUT pin (Pin 13). The
VOUT pin connects to an internal balun, which is capable of
driving a 50 Ω load. For applications requiring 50 Ω output
impedance, external matching is needed (see Figure 8 for S22
performance). The internal balun provides a low dc path to
ground. In most situations, the VOUT pin should be ac-coupled
to the load.
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| ADL5372ACPZ-R21 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1500 MHz to 2500 MHz Quadrature Modulator |
| ADL5372ACPZ-R7 | 功能描述:IC QUADRA MOD 1.5/2.5GHZ 24LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 調(diào)制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 功能:調(diào)制器 LO 頻率:700MHz ~ 2.3GHz RF 頻率:700MHz ~ 2.3GHz P1dB:1dBm 底噪:-148dBm/Hz 輸出功率:-1dBm 電流 - 電源:46mA 電源電壓:2.7 V ~ 3.6 V 測試頻率:1.75GHz 封裝/外殼:28-WFQFN 裸露焊盤 包裝:帶卷 (TR) |
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| ADL5372ACPZ-WP | 制造商:Analog Devices 功能描述:QUADRATURE MOD 700MHZ 24LFCSP EP - Waffle Pack |
| ADL5372ACPZ-WP1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1500 MHz to 2500 MHz Quadrature Modulator |
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