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參數(shù)資料
| 型號： | ADF4219L |
| 英文描述： | ADF4217L/18L/19L: Dual Low Power Frequency Synthesizers Data Sheet (Rev. B. 7/02) |
| 中文描述： | ADF4217L/18L/19L：雙低功耗頻率合成器數(shù)據(jù)手冊（啟示二7月2日） |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 400K |
| 代理商： | ADF4219L |
REV. A
–10–
ADF4212L
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = PB + A). The dual modulus prescaler, operating at CML
levels, takes the clock from the RF/IF input stage and divides it
down to a manageable frequency for the CMOS A and B
counters in the RF and IF sections. The prescaler in both sec-
tions is programmable. It can be set in software to 8/9, 16/17,
32/33, or 64/65. See Table IV and Table VI. It is based on a
synchronous 4/5 core.
RF/IF A and B Counters
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed-
back counter. The counters are specified to work when the
prescaler output is 200 MHz or less. Typically, they will work
with 250 MHz output from the prescaler. Thus, with an RF
input frequency of 2.5 GHz, a prescaler value of 16/17 is valid,
but a value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
(
f
P
B
A
f
R
VCO
REFIN
=
×
)
+
[
]
×
/
f
VCO
= Output frequency of external voltage controlled oscillator
(VCO)
= Preset modulus of dual modulus prescaler (8/9, 16/17,
and so on)
= Preset divide ratio of binary 13-bit counter (3 to 8191)
= Preset divide ratio of binary 6-bit swallow counter (0 to 63)
f
REFIN
= External reference oscillator frequency
R
= Preset divide ratio of binary 14-bit programmable reference
counter (1 to 16383)
P
B
A
TO PFD
N = BP + A
LOAD
LOAD
MODULUS
CONTROL
FROM RF
INPUT STAGE
12-BIT B
COUNTER
6-BIT A
COUNTER
PRESCALER
P/P+1
Figure 4. RF/IF A and B Counters
RF/IF R Counter
The 14-bit RF/IF R counter allows the input reference fre-
quency to be divided down to produce the input clock to the
phase frequency detector (PFD). Division ratios from 1 to
16,383 are allowed.
Phase Frequency Detector (PFD) and Charge Pump
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse. This is typically 3 ns. This pulse ensures
that there is no dead zone in the PFD transfer function and
gives a consistent reference spur level.
D1
Q1
CLR1
U1
U3
DELAY
HI
UP
D2
Q2
CLR2
U2
DOWN
+IN
HI
–IN
CHARGE
PUMP
CP
Figure 5. RF/IF PFD Simplified Schematic
MUXOUT and Lock Detect
The output multiplexer on the ADF4212L allows the user to
access various internal points on the chip. The state of MUXOUT
is controlled by P3, P4, P11, and P12. See Table III and Table V.
Figure 6 shows the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
Digital Lock Detect and Analog Lock Detect. Digital Lock
Detect is active high. It is set high when the phase error on three
consecutive Phase Detector cycles is less than 15 ns. It will stay
set high until a phase error of greater than 25 ns is detected on
any subsequent PD cycle.
The N-channel open-drain Analog Lock Detect should be oper-
ated with an external pull-up resistor of 10 k
nominal. When
lock has been detected, it is high with narrow, low-going pulses.
IF ANALOG LOCK DETECT
IF R COUNTER OUTPUT
IF N COUNTER OUTPUT
IF/RF ANALOG LOCK DETECT
RF R COUNTER OUTPUT
RF N COUNTER OUTPUT
RF ANALOG LOCK DETECT
MUX
CONTROL
MUXOUT
DV
DD
DGND
Figure 6. MUXOUT Schematic
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