參數(shù)資料
型號(hào)： ADF4219L
英文描述： ADF4217L/18L/19L: Dual Low Power Frequency Synthesizers Data Sheet (Rev. B. 7/02)
中文描述： ADF4217L/18L/19L：雙低功耗頻率合成器數(shù)據(jù)手冊(cè)（啟示二7月2日）
文件頁(yè)數(shù)： 1/20頁(yè)
文件大小： 400K
代理商： ADF4219L
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
Tel: 781/329-4700
www.analog.com
ADF4212L
Dual Low Power PLL
Frequency Synthesizer
FEATURES
I
DD
Total, 7.5 mA
Bandwidth RF/IF, 2.4 GHz/1.0 GHz
2.7 V to 3.3 V Power Supply
Separate VP Allows Extended Tuning Voltage
Programmable Dual Modulus Prescaler
RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Analog and Digital Lock Detect
Fastlock Mode
Power-Down Mode
20-Lead TSSOP and 20-Lead MLF Chip Scale Package
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Cable TV Tuners (CATV)
Communications Test Equipment
FUNCTIONAL BLOCK DIAGRAM
12-BIT IF
B-COUNTER
6-BIT IF
A-COUNTER
IF
PRESCALER
OUTPUT
MUX
IF
LOCK
DETECT
CHARGE
PUMP
RF
LOCK
DETECT
CHARGE
PUMP
14-BIT RF
R-COUNTER
14-BIT IF
R-COUNTER
OSCILLATOR
22-BIT
DATA
REGISTER
SDOUT
12-BIT RF
B-COUNTER
6-BIT RF
A-COUNTER
RF
PRESCALER
IF PHASE
FREQUENCY
DETECTOR
DGND
RF
AGND
RF
DGND
IF
AGND
IF
V
DD
1
V
DD
2
V
P
1
V
P
2
ADF4212L
IF
IN
REF
IN
CLOCK
DATA
LE
RF
IN
CP
RF
MUXOUT
CP
IF
R
SET
REFERENCE
IF CURRENT
SETTING
IFCP3 IFCP2 IFCP1
REFERENCE
RFCP3 RFCP2 RFCP1
REFERENCE
R
SET
FL
O
FL
O
SWITCH
RF PHASE
FREQUENCY
DETECTOR
GENERAL DESCRIPTION
The ADF4212L is a dual frequency synthesizer that can be used
to implement local oscillators (LO) in the up-conversion and
down-conversion sections of wireless receivers and transmitters.
It can provide the LO for both the RF and IF sections. It con-
sists of a low noise digital PFD (Phase Frequency Detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual modulus prescaler
(P/P + 1). The A (6-bit) and B (12-bit) counters, in conjunction
with the dual modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete PLL (Phase-Locked Loop) can be implemented
if the synthesizer is used with external loop filters and VCOs
(Voltage Controlled Oscillators).
Control of all the on-chip registers is via a simple 3-wire inter-
face with 1.8 V compatibility. The devices operate with a power
supply ranging from 2.7 V to 3.3 V and can be powered down
when not in use.
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