- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9108 > ADF4212LBRUZ-RL7 (Analog Devices Inc)IC PLL FREQ SYNTHESIZER 20TSSOP PDF資料下載
參數(shù)資料
| 型號： | ADF4212LBRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/頻率合成器（RF/IF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Data Sheet
ADF4212L
Rev. E | Page 21 of 28
IF Power-Down
Table 9 shows the power-down bits in the ADF4212L.
IF Fastlock
The IF CP gain bit (P8) of the IF N counter latch register in the
ADF4212L is the fastlock enable bit. Only when P8 is set to 1 is
IF fastlock enabled. When fastlock is enabled, the IF CP current
is set to the maximum value. Also, an extra loop filter damping
resistor to ground is switched in using the FLO pin, thus
compensating for the change in loop characteristics while in
fastlock. Because the IF CP gain bit is contained in the IF N
counter, only one write is needed to both program a new output
frequency and initiate fastlock. To come out of fastlock, the IF
CP gain bit on the IF N counter latch register must be set to 0
(see Table 9).
RF SECTION
Programmable RF Reference (R) Counter
If Control Bits[C2: C1] = 10, the data is transferred from the
input shift register to the 15-bit RF R counter. Table 10 shows
the input shift register data format for the RF R counter and the
divide ratios possible.
RF Phase Detector Polarity
P9 sets the IF phase detector polarity. When the RF VCO
characteristics are positive, P9 should be set to 1. When they are
negative, it should be set to 0 (see Table 10).
RF Charge Pump Three-State
P10 puts the RF charge pump into three-state mode when
programmed to a 1. It should be set to 0 for normal operation
(see Table 10).
RF Program Modes
Table 10 shows how to set up the program modes in the
RF Charge Pump Currents
RFCP2, RFCP1, and RFCP0 program the current setting for the
RF charge pump. See Table 10.
Programmable RF N Counter
If Control Bits[C2:C1] = 11, the data in the input register is
used to program the RF N (A + B) counter. The N counter
consists of a 6-bit swallow counter (A counter) and a 12-bit
programmable counter (B counter). Table 11 shows the input
register data format for programming the RF N counter and the
divide ratios that are possible.
RF Prescaler Value
P14 and P15 in the RF N counter latch set the RF prescaler
values. See Table 11.
RF Power-Down
Table 11 shows the power-down bits in the ADF4212L.
RF Fastlock
The RF CP gain bit (P17) of the RF N counter latch register in
the ADF4212L is the fastlock enable bit. Only when P17 is set to
1 is IF fastlock enabled. When fastlock is enabled, the RF CP
current is set to the maximum value. Also, an extra loop filter
damping resistor to ground is switched in using the FLO pin,
thus compensating for the change in loop characteristics while
in fastlock. Because the RF CP gain bit is contained in the RF N
counter, only one write is needed to both program a new output
frequency and initiate fastlock. To come out of fastlock, the RF
CP gain bit on the RF N counter latch register must be set to 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADF4106BRU-REEL | IC PLL FREQ SYNTHESIZER 16-TSSOP |
| ADF4212LBCPZ-RL | IC PLL FREQ SYNTHESIZER 20LFCSP |
| ADF4212BRUZ-RL | IC PLL FREQ SYNTHESIZER 20-TSSOP |
| ADF4212LBRUZ-RL | IC PLL FREQ SYNTHESIZER 20TSSOP |
| ADF4111BCPZ-RL7 | IC PLL FREQ SYNTHESIZER 20-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4213 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual RF/IF PLL Frequency Synthesizers |
| ADF4213BCP | 制造商:Rochester Electronics LLC 功能描述:DUAL PLL 2.5/1.1 GHZ - Bulk 制造商:Analog Devices 功能描述: |
| ADF4213BCPZ | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述: |
| ADF4213BCPZ-RL | 功能描述:IC PLL FREQ SYNTHESIZER 20LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ADF4213BCPZ-RL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin LFCSP EP T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。