參數(shù)資料
型號(hào): ADF4212LBCPZ-RL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 1/28頁(yè)
文件大?。?/td> 0K
描述: IC PLL FREQ SYNTHESIZER 20LFCSP
標(biāo)準(zhǔn)包裝: 5,000
類型: 時(shí)鐘/頻率合成器(RF/IF)
PLL:
輸入: CMOS,TTL
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 3:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無(wú)
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 20-LFCSP-VQ
包裝: 帶卷 (TR)
Dual Low Power PLL
Frequency Synthesizer
Data Sheet
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2002–2014 Analog Devices, Inc. All rights reserved.
FEATURES
IDD total: 7.5 mA
Bandwidth RF/IF: 2.4 GHz/1.0 GHz
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable dual modulus prescaler
RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Fastlock mode
Power-down mode
20-lead TSSOP and 20-lead LFCSP packages
APPLICATIONS
Wireless handsets (GSM, PCS, DCS, DSC1800, CDMA,
WCDMA)
Base stations for wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless LANS
Cable TV tuners (CATV)
Communications test equipment
GENERAL DESCRIPTION
The ADF4212L is a dual frequency synthesizer that can be used
to implement local oscillators (LO) in the up-conversion and
down-conversion sections of wireless receivers and transmitters.
It can provide the LO for both the RF and IF sections. It consists
of a low noise digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual modulus prescaler (P/P + 1). The
A (6-bit) and B (12-bit) counters, in conjunction with the dual
modulus prescaler (P/P + 1), implement an N divider (N = BP +
A). In addition, the 15-bit reference counter (R counter) allows
selectable REFIN frequencies at the PFD input. A complete phase-
locked loop (PLL) can be implemented if the synthesizer is used
with external loop filters and voltage controlled oscillators (VCOs).
Control of all the on-chip registers is via a simple 3-wire
interface with 1.8 V compatibility. The devices operate with a
power supply ranging from 2.7 V to 3.3 V and can be powered
down when not in use.
FUNCTIONAL BLOCK DIAGRAM
RFIN
IF
PRESCALER
DGNDRF
AGNDRF
DGNDIF
AGNDIF
RSET
FLO SWITCH
FLO
RSET
VDD1
VDD2
VP1
VP2
REFIN
IFIN
CLK
ADF4212L
DATA
LE
22-BIT
DATA
REGISTER
SDOUT
15-BIT RF
R-COUNTER
15-BIT IF
R-COUNTER
12-BIT RF
B-COUNTER
12-BIT IF
B-COUNTER
IF PHASE
FREQUENCY
DETECTOR
02774-
001
IF
LOCK
DETECT
IFCP3
IFCP2
IF CURRENT
SETTING
CHARGE
PUMP
REFERENCE
IFCP1
RFCP3 RFCP2
OUTPUT
MUX
REFERENCE
RF PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
RFCP1
6-BIT RF
A-COUNTER
6-BIT IF
A-COUNTER
RF
PRESCALER
OSCILLATOR
RF
LOCK
DETECT
MUXOUT
CPIF
CPRF
Figure 1.
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