- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9108 > ADF4212LBCPZ-RL7 (Analog Devices Inc)IC PLL FREQ SYNTHESIZER 20LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADF4212LBCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 時鐘/頻率合成器（RF/IF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
ADF4212L
Data Sheet
Rev. E | Page 24 of 28
INTERFACING
The ADF4212L has a simple SPI-compatible interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When latch enable (LE) goes high, the 22 bits that have
been clocked into the input register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 6 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 909 kHz or
one update every 1.1 μs, which is more than adequate for systems
that have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 33 shows the interface between the ADF4212L and the
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI (serial
port interface) master mode with CPHA = 0. To initiate the
operation, the I/O port driving LE is brought low. Each latch of
the ADF4212L needs a 24-bit word. This is accomplished by
writing three 8-bit bytes from the microconverter to the device.
When the third byte has been written, the LE input should be
brought high to complete the transfer.
When first applying power to the ADF4212L, four writes (one
each to the R counter latch and the N counter latch for both the
IF and RF sides) are required for the output to become active.
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed is 180 kHz.
ADSP-2181 Interface
Figure 34 shows the interface between the ADF4212L and the
ADSP-21xx digital signal processor. As previously described,
the ADF4212L needs a 24-bit serial word for each latch write.
The easiest way to accomplish this with the ADSP-21xx family
is to use the autobuffered transmit mode of operation with
alternate framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated. Set
up the word length for eight bits and use three memory locations
for each 24-bit word. To program each 24-bit latch, store the
three 8-bit bytes, enable the autobuffered mode, and then write
to the transmit register of the DSP. This last operation initiates
the autobuffer transfer.
ADF4212L
CLK
DATA
LE
MUXOUT
(LOCK DETECT)
ADuC812
SCLOCK
MOSI
I/O PORTS
02774-
038
Figure 33. ADuC812 to ADF4212L Interface
ADF4212L
CLK
MUXOUT
(LOCK DETECT)
ADSP-21xx
SCLOCK
I/O FLAGS
DATA
DT
LE
TFS
02774-
039
Figure 34. ADSP-21xx to ADF4212L Interface
PCB DESIGN GUIDELINES FOR LEAD FRAME CHIP
SCALE PACKAGE
The lands on the LFCSP (CP-20-6) are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This ensures
that the solder joint size is maximized. The bottom of the LFCSP
has a central thermal pad.
The thermal pad on the PCB should be at least as large as the
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they
should be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter should be between 0.3 mm and 0.33 mm, and
the via barrel should be plated with 1 oz copper to plug the via.
The user should connect the PCB thermal pad to PCB ground.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADF4212LBRUZ-RL7 | IC PLL FREQ SYNTHESIZER 20TSSOP |
| ADF4106BRU-REEL | IC PLL FREQ SYNTHESIZER 16-TSSOP |
| ADF4212LBCPZ-RL | IC PLL FREQ SYNTHESIZER 20LFCSP |
| ADF4212BRUZ-RL | IC PLL FREQ SYNTHESIZER 20-TSSOP |
| ADF4212LBRUZ-RL | IC PLL FREQ SYNTHESIZER 20TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4212LBRU | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP |
| ADF4212LBRU-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP T/R 制造商:Analog Devices 功能描述:PLL FREQ SYNTHESIZER DUAL 20TSSOP - Tape and Reel |
| ADF4212LBRU-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 20-Pin TSSOP T/R 制造商:Analog Devices 功能描述:PLL FREQ SYNTHESIZER DUAL 20TSSOP - Tape and Reel |
| ADF4212LBRUZ | 功能描述:IC PLL FREQ SYNTHESIZER 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4212LBRUZ-RL | 功能描述:IC PLL FREQ SYNTHESIZER 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。