- 您現(xiàn)在的位置：買賣IC網 > PDF目錄378285 > ADC14061 (National Semiconductor Corporation) Low Dropout Linear 2-cell Li-Ion Charge Controller with AutoCompTM, 8.4V 8-SOIC -20 to 70 PDF資料下載
參數(shù)資料
| 型號： | ADC14061 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Low Dropout Linear 2-cell Li-Ion Charge Controller with AutoCompTM, 8.4V 8-SOIC -20 to 70 |
| 中文描述： | 自校準14位，250 MSPS的，390毫瓦的A / D轉換器 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 471K |
| 代理商： | ADC14061 |
Applications Information
(Continued)
The sign bit of the output word will be a logic low when V
+
is greater than V
. When V
+ is less than V
IN
, the sign
bit of the output word will be a logic high.
For single ended operation, one of the analog inputs should
be connected to V
. However, SNR and SINAD are re-
duced by about 12dB with a single ended input as compared
with differential inputs.
An input voltage of V
= (V
+) (V
) = 0 will be inter-
preted as mid-scale and will thus be converted to
00,0000,0000,0000, plus any offset error.
The V
+ and the V
inputs of the ADC14061 consist of an
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 12 pF when the clock is low,
and 28 pF when the clock is high. It is recommended that the
ADC14061 be driven with a low impedance source of 100
Ohms or less.
Asimple application circuit is shown in Figure 6and Figure 7
Here we use two LM6172 dual amplifiers to provide a bal-
anced input to the ADC14061. Note that better noise perfor-
mance is achieved when V
REF
+
IN
voltage is forced with a
well-bypassed resistive divider. The resulting offset and off-
set drift is minimal.
Since a dynamic capacitance is more difficult to drive than is
a fixed capacitance, choose driving amplifiers carefully. The
CLC427, CLC440, LM6152, LM6154, LM6172, LM6181 and
LM6182 are excellent amplifiers for driving the ADC14061.
1.4 V
CM
Analog Inputs
The V
CM
input of the ADC14061 is internally biased to 40%
of the V
A
supply with on-chip resistors, as shown in Figure 5
The V
pin must be bypassed to prevent any power supply
noise from modulating this voltage. Modulation of the V
potential will result in the introduction of noise into the input
signal. The advantage of simply bypassing V
(without
driving it) is the circuit simplicity. On the other hand, if the V
A
supply can vary for any reason, V
will also vary at a rate
and amplitude related to the RC filter created by the bypass
capacitor and the internal divider resistors. However, perfor-
mance of this approach will be adequate for many
applications.
By forcing V
CM
to a fixed potential, you can avoid the prob-
lems mentioned above. One such approach is to buffer the
2.0 Volt reference voltage to drive the V
input, holding it at
a constant potential as shown in Figure 6and Figure 8 If the
reference voltage is different from the desired V
, that de-
sired V
voltage may be derived from the reference or from
another stable source.
Note that the buffer used for this purpose should be a slow,
low noise amplifier. The LMC660, LMC662, LMC272 and
LMC7101 are good choices for driving the V
CM
pin of the
ADC14061.
If it is desired to use a multiplexer at the analog input, that
multiplexer should be switched at the rising edge of the clock
signal.
2.0 DIGITAL INPUTS
Digital Inputs consist of CLOCK, RESET, CAL, RD and PD.
All digital input pins should remain stable from the fall of the
clock until 30ns after the fall of the clock to minimize digital
noise corruption of the input signal on the die.
2.1 The CLOCK
signal drives an internal phase delay loop to
create timing for theADC. Drive the clock input with a stable,
low phase jitter clock signal in the range of 300 kHz to 2.5
MHz. The trace carrying the clock signal should be as short
as possible. This trace should not cross any other signal line,
analog or digital, not even at 90.
The CLOCK signal also drives the internal state machine. If
the clock is interrupted, the data within the pipeline could be-
come corrupted.
A 100 Ohm damping resistor should be placed in series with
the CLOCK pin to prevent signal undershoot at that input.
2.2 The RESET
input is level sensitive and must be pulsed
high for at least two clock cycles to reset the ADC after
power-up and before calibration (See Timing Diagram 2).
2.3 The CAL
input is level sensitive and must be pulsed high
for at least two clock cycles to begin ADC calibration (See
Timing Diagram 2). Reset the ADC14061 before calibrating.
Re-calibrate after the temperature has changed by more
than 50C since the last calibration was performed and after
return from power down.
During calibration, use the same clock frequency that will be
used for conversions to avoid excessive offset errors.
Calibration takes 272,800 clock cycles. Irrelevant data may
appear at the data outputs during RESET or CAL and for 13
clock cycles thereafter. Calibration should not be started until
the reference outputs have settled (100mS with 1μF capaci-
tors on these outputs) after power up or coming out of the
power down mode.
2.4 RD
pin is used to READ the conversion data. When the
RD pin is low, the output buffers go into the active state.
When the RD input is high, the output buffers are in the high
impedance state.
2.5 The PD
pin, when low, holds the ADC14061 in a
power-down mode where power consumption is typically
less than 2mW to conserve power when the converter is not
being used. The ADC14061 will begin normal operation
within t
after this pin is brought high, provided a valid
CLOCK input is present. Power dissipation during shut-down
is not affected by the clock frequency, or by whether there is
a clock signal present. The data in the pipeline is corrupted
while in the power down mode. TheADC14061 should be re-
set and calibrated upon returning to normal operation after a
power down.
3.0 OUTPUTS
The ADC14061 has four analog outputs: V
+
V
, V
and V
.There are 15 digital outputs:
EOC (End of Conversion) and 14 Data Output pins.
,
DS100103-21
FIGURE 5. V
input to the ADC14061 V
is set to
40% of V
A
with on-chip resistors. Performance is
improved when V
CM
is driven with a stable, low
impedance source
A
www.national.com
14
相關PDF資料 |
PDF描述 |
|---|---|
| ADC14071CIVBH | 14-Bit, 7 MSPS, 380 mW A/D Converter |
| ADC14071 | 14-Bit, 7 MSPS, 380 mW A/D Converter |
| ADC14071EVAL | 14-Bit, 7 MSPS, 380 mW A/D Converter |
| ADC14161 | Low Dropout Linear 2-cell Li-Ion Charge Controller with AutoCompTM, 8.4V 8-SOIC -20 to 70 |
| ADC14161CIVT | Low-Distortion, Self-Calibrating 14-Bit, 2.5 MSPS, 390 mW A/D Converter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADC14061EVAL | 功能描述:BOARD EVALUATION FOR ADC14061 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| ADC14071A WAF | 制造商:Texas Instruments 功能描述: |
| ADC1410S065/DB,598 | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 ADC DEMO BOARD RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADC1410S065F1-DB | 功能描述:ADC1410S065 - 14 Bit 65M Samples per Second Analog to Digital Converter (ADC) Evaluation Board 制造商:idt, integrated device technology inc 系列:- 零件狀態(tài):過期 A/D 轉換器數(shù):1 位數(shù):14 采樣率（每秒）:65M 數(shù)據(jù)接口:SPI 輸入范圍:2 Vpp 不同條件下的功率（典型值）:380mW @ 65MSPS 使用的 IC/零件:ADC1410S065 所含物品:板 標準包裝:1 |
| ADC1410S065F2-DB | 功能描述:ADC1410S065 - 14 Bit 65M Samples per Second Analog to Digital Converter (ADC) Evaluation Board 制造商:idt, integrated device technology inc 系列:- 零件狀態(tài):過期 A/D 轉換器數(shù):1 位數(shù):14 采樣率（每秒）:65M 數(shù)據(jù)接口:SPI 輸入范圍:2 Vpp 不同條件下的功率（典型值）:380mW @ 65MSPS 使用的 IC/零件:ADC1410S065 所含物品:板 標準包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復。