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參數(shù)資料
| 型號(hào)： | ADC12191 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold(12位10 MHz可自行校對(duì)的管線式帶內(nèi)部采樣和保持功能A/D轉(zhuǎn)換器) |
| 中文描述： | 12位，10 MHz的自校準(zhǔn)，流水線A / D轉(zhuǎn)換器，內(nèi)置采樣 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 278K |
| 代理商： | ADC12191 |
DC and Logic Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, V
A
= V
D
= V
D
I/O = +5V, PD = +5V, V
REF
= +2.0V,
f
CLK
= 10 MHz, C
L
= 50 pF/pin. After Auto-Cal at Temperature.
Boldface limits apply for T
A
= T
MIN
to T
MAX
;
all other limits
T
A
= T
J
= 25C (Note 7) (Note 8) and (Note 9)
Symbol
Parameter
Conditions
Typical
(Note
10)
Limits
(Note
11)
Units
(Limits)
CLK, OE Digital Input Characteristics
V
IH
Logical “1” Input Voltage
V
IL
Logical “0” Input Voltage
I
IH
Logical “1” Input Current
I
IL
Logical “0” Input Current
C
IN
V
IN
Input Capacitance
D0 - D11 Digital Output Characteristics
V
OH
Logical “1” Output Voltage
V
OL
Logical “0” Output Voltage
I
OZ
TRI-STATE
Output Current
V+ = 5.25V
V+ = 4.75V
V
IN
= 5.0V
V
IN
= 0V
2.0
0.8
V(min)
V(min)
μA
μA
pF
5
5
8
I
OUT
= 1mA
I
OUT
= 1.6mA
V
OUT
= 3V or 5V
V
OUT
= 0V
4
V (min)
V (max)
μA
μA
mA(min)
0.4
10
10
+I
SC
Output Short Circuit Source
Current
Output Short Circuit Sink Current
Power Supply Characteristics
VDDO= 3V, V
OUT
= 0V
14
I
SC
VDDO= 3V, V
OUT
= V
O
16
mA(min)
I
A
Analog Supply Current
PD = VDDO
PD = DGND
PD = VDDO
PD = DGND
PD = VDDO
PD = DGND
2.5
45
0.5
2
15
235
4
55
2
3
30
290
mA(max)
mA(max)
mA(max)
mA(max)
mW(max)
mW(max)
I
D
Digital Supply Current
Total Power Consumption
AC Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, V
A
= V
D
= V
D
I/O = +5V, PD = +5V, V
= +2.0V,
f
CLK
= 10 MHz, C
= 50 pF/pin. After Auto-Cal at Temperature.
Boldface limits apply for T
A
= T
MIN
to T
MAX
;
all other limits
T
A
= T
J
= 25C (Note 7) (Note 8) and (Note 10)
Symbol
Parameter
Conditions
Typical
(Note
10)
1
Limits
(Note
11)
Units
(Limits)
f
CLK
Clock Frequency
MHz(min)
MHz(max)
%
Clock
Cycles
10
Clock Duty Cycle
50
t
CONV
Conversion Latency
10
t
OD
Data output delay after rising clk
edge
Data outputs into Tristate mode
Data outputs active after Tristate
Calibration request pulse width
Ready Low after CAL request
Calibration cycle
Power-down pulse width
Ready Low after PD request
Power down mode exit cycle
40
ns
t
DIS
t
EN
t
WCAL
t
RDYC
t
CAL
t
WPD
t
RDYPD
t
PD
21
21
nA (max)
ns (max)
Tclk(min)
Tclk
Tclk
Tclk(min)
Tclk
Tclk
3
3
4000
3
3
4000
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2:
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
A
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