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參數(shù)資料
| 型號(hào)： | ADC12191 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold(12位10 MHz可自行校對(duì)的管線式帶內(nèi)部采樣和保持功能A/D轉(zhuǎn)換器) |
| 中文描述： | 12位，10 MHz的自校準(zhǔn)，流水線A / D轉(zhuǎn)換器，內(nèi)置采樣 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 278K |
| 代理商： | ADC12191 |
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Applications Information
(Continued)
2.3 OE Pin
The OE pin is used to control the state of the
outputs. When the OE pin is low, the output buffers go into
the active state. When the OE input is high, the output
buffers are in the high impedance state.
2.4 PD Pin
The PD pin, when high, holds the ADC12191 in
a power-down mode where power consumption is typically
less than 15 mW to conserve power when the converter is
not being used. The ADC12191 will begin normal operation
within t
after this pin is brought low, provided a valid
CLOCK input is present. The data in the pipeline is corrupted
while in the power down mode. The ADC12191 should be
re-calibrated after a power-down cycle to ensure optimum
performance.
3.0 Outputs
The ADC12191 has three analog outputs: reference output
voltages V
, V
, and V
. There are 14 digital outputs:
12 Data Output pins, Ready and OR (Out of Range).
3.1 Reference Output Voltages
The reference output
voltages are made available only for the purpose of
bypassing with capacitors to a clean analog ground. The
recommended bypass capacitors are 0.1μF ceramic chip
capacitors. Do not load these pins.
3.2 Ready Output
The Ready output goes high to indicate
that the converter is ready for operation. This signal will go
low when the converter is in Calibration or Power Down
mode.
3.3 OR (Out of Range) Output
The OR output goes high
when the analog input is below GND or above V
. This
output is low when the input signal is in the valid range of
operation (0V
≤
V
IN
≤
V
REF
).
3.4 Data Outputs
The Data Outputs are TTL/CMOS
compatible. The output data format is 12 bits straight binary.
Minimizing the digital output currents will help to minimize
noise due to output switching. This can be done by
connecting buffers between the ADC outputs and any other
circuitry. Only one buffer input should be connected to each
output. Additionally, inserting series resistors of 47 to 56
Ohms right at the digital outputs, close to the ADC pins, will
isolate the outputs from other circuitry and limit output
currents.
4.0 Power Supply Considerations
Each power pin should be bypassed with a parallel
combination of a 10μF capacitor and a 0.1μF ceramic chip
capacitor. The chip capacitors should be within 1/2
centimeter of the power pins. Leadless chip capacitors are
preferred because they provide low lead inductance.
The converter’s digital logic supply (V
) should be well
isolated from the supply that is used for other digital circuitry
on the board. A common power supply should be used for
both V
(analog supply) and V
(digital supply), and each of
these supply pins should be separately bypassed with a
0.1μF ceramic capacitor and a low ESR 10μF capacitor. A
ferrite bead or inductor should be used between V
and V
D
to prevent noise coupling from the digital supply into the
analog circuit.
V
I/O is the power pin for the output driver. This pin may be
supplied with a potential between 3V and 5V. This makes it
easy to interface the ADC12191 with 3V or 5V logic families.
Powering the V
I/O from 3 Volts will also reduce power
consumption and noise generation due to output switching.
DO NOT operate the V
I/O at a voltage higher than V
or
V
A
!
All power supplies connected to the device should be
applied simultaneously.
As is the case with all high speed converters, the ADC12191
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be minimized, keeping it below
100mV P-P.
A
www.national.com
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