參數(shù)資料
型號: ADC10321
廠商: National Semiconductor Corporation
英文描述: 10-Bit, 20MSPS, 98mW A/D Converter with Internal Sample and Hold(10位20MSPS, 98 mW帶內(nèi)部采樣和保持功能A/D轉(zhuǎn)換器)
中文描述: 10位,20MSPS,98mW的A / D轉(zhuǎn)換器內(nèi)部采樣和保持(10位20MSPS,98毫瓦帶內(nèi)部采樣和保持功能的A / D轉(zhuǎn)換器)
文件頁數(shù): 10/16頁
文件大?。?/td> 395K
代理商: ADC10321
Timing Diagram
Functional Description
The ADC10321 maintains excellent dynamic performance
for input signals up to half the clock frequency. The use of an
internal sample-and-hold amplifier (SHA) enables sustained
dynamic performance for signals of input frequency beyond
the clock rate, lowers the converter’s input capacitance and
reduces the number of external components required.
The analog signal at V
that is within the voltage range set
by V
+ S and V
S are digitized to ten bits at up to 25
MSPS. Input voltages below V
S will cause the output
word to consist of all zeroes. Input voltages above V
REF
+ S
will cause the output word to consist of all ones. V
REF
+ S has
a range of 2.3 to 4.0 Volts, while V
S has a range of 1.3
to 3.0 Volts. V
REF
+ S should always be at least 1.0 Volt more
positive than V
REF
S.
Data is acquired at the falling edge of the clock and the
digital equivalent of that data is available at the digital out-
puts 2.0 clock cycles plus t
later. The ADC10321 will
convert as long as the clock signal is present at pin 9 and the
PD pin is low. The Output Enable pin (OE), when low,
enables the output pins. The digital outputs are in the high
impedance state when the OE pin is low or the PD pin is
high.
DS100897-15
FIGURE 1. ADC10321 Timing Diagram
DS100897-17
FIGURE 2. AC Test Circuit
DS100897-16
FIGURE 3. t
EN
, t
DIS
Test Circuit
A
www.national.com
10
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