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參數(shù)資料
| 型號： | ADC101S101EVAL |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 |
| 中文描述： | 1MSPS，12/10/8位的A / D轉(zhuǎn)換器采用SOT - 23 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 621K |
| 代理商： | ADC101S101EVAL |
Applications Information
1.0 ADC081S051 OPERATION
The ADC081S051 are successive-approximation analog-to-
digital converters designed around a charge-redistribution
digital-to-analog converter. Simplified schematics of the
ADC081S051 in both track and hold operation are shown in
Figures 3 and 4, respectively. In Figure 3, the device is in
track mode: switch SW1 connects the sampling capacitor to
the input, and SW2 balances the comparator inputs. The
device is in this state until CS is brought low, at which point
the device moves to hold mode.
Figure 4 shows the device in hold mode: switch SW1 con-
nects the sampling capacitor to ground, maintaining the
sampled voltage, and switch SW2 unbalances the compara-
tor. The control logic then instructs the charge-redistribution
DAC to add or subtract fixed amounts of charge from the
sampling capacitor until the comparator is balanced. When
the comparator is balanced, the digital word supplied to the
DAC is the digital representation of the analog input voltage.
The device moves from hold mode to track mode on the 13th
rising edge of SCLK.
2.0 USING THE ADC081S051
The serial interface timing diagram for the ADC081S051 is
shown in Figure 2. CS is chip select, which initiates conver-
sions on the ADC081S051 and frames the serial data trans-
fers. SCLK (serial clock) controls both the conversion pro-
cess and the timing of serial data. SDATA is the serial data
out pin, where a conversion result is found as a serial data
stream.
Basic operation of the ADC081S051 begins with CS going
low, which initiates a conversion process and data transfer.
Subsequent rising and falling edges of SCLK will be labelled
with reference to the falling edge of CS; for example, "the
third falling edge of SCLK" shall refer to the third falling edge
of SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE,
and the converter moves from track mode to hold mode. The
input signal is sampled and held for conversion on the falling
edge of CS. The converter moves from hold mode to track
mode on the 13th rising edge of SCLK (see Figure 2). The
SDATA pin will be placed back into TRI-STATE after the 16th
falling edge of SCLK, or at the rising edge of CS, whichever
occurs first. After a conversion is completed, the quiet time
t
QUIET
must be satisfied before bringing CS low again to
begin another conversion.
Sixteen SCLK cycles are required to read a complete
sample from the ADC081S051. The sample bits (including
any leading or trailing zeroes) are clocked out on falling
edges of SCLK, and are intended to be clocked in by a
receiver on subsequent falling edges of SCLK. The
ADC081S051 will produce three leading zero bits on SDATA,
followed by eight data bits, most significant first. After the
data bits, the ADC081S051 will clock out four trailing zeros.
If CS goes low before the rising edge of SCLK, an additional
(fourth) zero bit may be captured by the next falling edge of
SCLK.
20145509
FIGURE 3. ADC081S051 in Track Mode
20145510
FIGURE 4. ADC081S051 in Hold Mode
A
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