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參數(shù)資料
| 型號(hào)： | ADC101S101EVAL |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 |
| 中文描述： | 1MSPS，12/10/8位的A / D轉(zhuǎn)換器采用SOT - 23 |
| 文件頁數(shù)： | 4/13頁 |
| 文件大小： | 621K |
| 代理商： | ADC101S101EVAL |
ADC081S051 Converter Electrical Characteristics
(Note 9) (Continued)
The following specifications apply for V
= +2.7V to 5.25V, GND = 0V, f
= 4 MHz to 10 MHz,
f
= 200 kSPS to 500 kSPS, unless otherwise noted.
Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
=
25C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 9)
Units
ANALOG INPUT CHARACTERISTICS
V
IN
Input Range
I
DCL
DC Leakage Current
0 to V
A
V
±
1
μA (max)
pF
pF
C
INA
Input Capacitance
Track Mode
Hold Mode
30
4
DIGITAL INPUT CHARACTERISTICS
V
IH
Input High Voltage
V
A
= +5.25V
V
A
= +5.25V
V
A
= +3.6V
V
IN
= 0V or V
A
2.4
0.8
0.4
±
1
4
V (min)
V (max)
V (max)
μA (max)
pF (max)
V
IL
Input Low Voltage
I
IN
C
IND
DIGITAL OUTPUT CHARACTERISTICS
Input Current
Digital Input Capacitance
±
0.1
2
V
OH
Output High Voltage
I
SOURCE
= 200 μA
I
SOURCE
= 1 mA
I
SINK
= 200 μA
I
SINK
= 1 mA
V
A
0.03
V
A
0.1
0.03
0.1
V
A
0.2
V (min)
V
V (max)
V
V
OL
Output Low Voltage
0.4
I
OZH
,
I
OZL
C
OUT
TRI-STATE
Leakage Current
±
0.1
±
10
μA (max)
TRI-STATE
Output Capacitance
Output Coding
POWER SUPPLY CHARACTERISTICS (C
L
= 10 pF)
2
4
pF (max)
Straight (Natural) Binary
V
A
Supply Voltage
2.7
5.25
V (min)
V (max)
I
A
Supply Current, Normal Mode
(Operational, CS low)
V
A
= +5.25V,
f
SAMPLE
= 200 kSPS
V
A
= +3.6V,
f
SAMPLE
= 200 kSPS
f
SCLK
= 0 MHz, V
A
= +5.25V
f
SAMPLE
= 0 kSPS
V
A
= +5.25V, f
SCLK
= 10MHz,
f
SAMPLE
= 0 kSPS
V
A
= +5.25V
V
A
= +3.6V
f
SCLK
= 0 MHz, V
A
= +5.25V
f
SAMPLE
= 0 kSPS
V
A
= +5.25V, f
SCLK
= 10 MHz,
f
SAMPLE
= 0 kSPS
2.0
2.4
mA (max)
0.8
1.0
mA (max)
Supply Current, Shutdown (CS high)
0.5
μA
22
μA
P
D
Power Consumption, Normal Mode
(Operational, CS low)
10.5
2.9
12.6
3.6
mW (max)
mW (max)
Power Consumption, Shutdown (CS
high)
2.6
μW
0.12
mW
AC ELECTRICAL CHARACTERISTICS
f
SCLK
Clock Frequency
(Note 8)
4
10
200
500
16
40
60
400
20
MHz (min)
MHz (max)
kSPS (min)
kSPS (max)
SCLK cycles
% (min)
% (max)
ns (max)
SCLK cycles
f
S
Sample Rate
(Note 8)
50
t
CONV
Conversion Time
DC
SCLK Duty Cycle
f
SCLK
= 10 MHz
50
t
ACQ
Track/Hold Acquisition Time
Throughput Time
Acquisition Time + Conversion Time
A
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