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參數(shù)資料
| 型號： | ADC08061CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 500 ns A/D Converter with S/H Function and Input Multiplexer |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ADC08061CIWM |
AC Electrical Characteristics
(Continued)
The following specifications apply for V
+
= 5V, t
= t
= 10 ns, V
REF+
= 5V, V
REF
= 0V unless otherwise specified.
Bold-
face limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
J
= 25C.
Symbol
Parameter
Condition
Typical
(Note 7)
200
400
500
Limits
(Note 8)
250
400
560
Units
(Limit)
ns (min)
ns (max)
ns (max)
t
RDW
RD Width
Mode Pin to GND; (Figure 5)
t
CONV
WR -RD Mode Conversion Time
(t
WR
+ t
RD
+ t
ACC1
)
RD Mode Conversion Time
Access Time (Delay from Falling
Edge of RD to Output Valid)
Access Time (Delay from
Falling Edge
of RD to Output Valid)
Mode Pin to V
+
; (Figure 2)
t
CRD
t
ACCO
Mode Pin to GND; (Figure 1)
C
L
≤
100 pF
Mode Pin to GND; (Figure 1)
C
L
≤
10 pF
C
L
= 100 pF
Mode Pin to V
+
, t
RD
≤
t
INTL
(Figure 2)
C
L
≤
10 pF
C
L
= 100 pF
t
RD
>
t
INTL
; (Figures 3, 4)
R
L
= 3 k
, C
L
= 10 pF
655
640
900
900
ns (max)
ns (max)
t
ACC1
45
50
110
ns (max)
t
ACC2
Access Time (Delay from
Falling Edge
of RD to Output Valid)
TRI-STATE
Control (Delay from
Rising Edge of RD to HI-Z State)
TRI-STATE Control (Delay from
Rising Edge of RD to HI-Z State)
Delay from Rising Edge of
WR to Falling Edge of INT
Delay from Rising Edge of
RD to Rising Edge of INT
Delay from Rising Edge of
WR to Rising Edge of INT
Delay from CS to RDY
25
30
55
ns (max)
t
0H
30
60
ns (max)
t
1H
R
L
= 3 k
, C
L
= 10 pF
30
60
ns (max)
t
INTL
(Figures 3, 4)
Mode Pin = V
+
, C
L
= 50 pF
C
L
= 50 pF; (Figures 1, 2, 3, 4)
2b, and 4 )
C
L
= 50 pF; (Figure 4)
520
690
ns (max)
t
INTH
50
95
ns (max)
t
INTH
45
95
ns (max)
t
RDY
Mode Pin = 0V, C
L
= 50 pF,
R
L
= 3 k
(Figure 1)
R
L
= 3 k
, C
L
= 100 pF;
(Figure 4)
Mode Pin = V
+
, t
RD
≤
t
INTL
;
(Figure 3)
(Figures 1, 2, 3, 4, 5)
25
45
ns (max)
t
ID
Delay from INT to Output Valid
0
15
ns (max)
t
RI
Delay from RD to INT
60
115
ns (max)
t
N
Time between End of RD
and Start of New Conversion
Channel Address Hold Time
Channel Address Setup Time
CS Setup Time
CS Hold Time
Analog Input Capacitance
Logic Output Capacitance
Logic Input Capacitance
50
50
ns (min)
t
AH
t
AS
t
CSS
t
CSH
C
VIN
C
OUT
C
IN
(Figures 1, 2, 3, 4, 5)
(Figures 1, 2, 3, 4, 5)
(Figures 1, 2, 3, 4, 5)
(Figures 1, 2, 3, 4, 5)
10
0
0
0
25
5
5
60
0
0
0
ns (min)
ns (max)
ns (max)
ns (min)
pF
pF
pF
DC Electrical Characteristics
The following specifications apply for V
+
= 5V unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
V
IH
Logic “1” Input Voltage
V
+
= 5.5V
Mode Pin
ADC08062
CS, WR, RD, A0 Pins
ADC08061
CS, WR, RD Pins
3.5
V (min)
2.2
V (min)
2.0
V (min)
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