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參數(shù)資料
| 型號： | ADC08061CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 500 ns A/D Converter with S/H Function and Input Multiplexer |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ADC08061CIWM |
Application Information
(Continued)
have a voltage drop of 1/256 of the total reference voltage
(V
V
) across them. The remaining resistors make
up the
MSB Ladder
. They are made up of eight groups of
four resistors connected in series. Each MSB Ladder section
has
1
8
of the total reference voltage across it. Within a given
MSB Ladder section, each of the MSB resistors has 8/256,
or 1/32 of the total reference voltage across it. Tap points are
found between all of the resistors in both the MSB and LSB
Ladders. Through the Comparator Multiplexer these tap
points can be connected, in groups of eight, to the eight com-
parators shown at the right of Figure 6 This function pro-
vides the necessary reference voltages to the comparators
during each flash conversion.
The six comparators, seven-resistor string (estimator DAC),
and Estimator Decoder at the left of Figure 6 form the Volt-
age Estimator. The estimator DAC connected between
V
and V
generates the reference voltages for the
six Voltage Estimator comparators. These comparators per-
form a very low resolution A/D conversion to obtain an “esti-
mate” of the input voltage. This estimate is then used to con-
trol the Comparator Multiplexer, connecting the appropriate
MSB Ladder section to the eight flash comparators. Only 14
comparators, six in the Voltage Estimator and eight in the
flash converter, are needed to achieve the full eight-bit reso-
lution, instead of 32 comparators that would be needed by
traditional half-flash methods.
A conversion begins with the Voltage Estimator comparing
the analog input signal against the six tap voltages on the es-
timator DAC. The estimator decoder then selects one of the
groups of tap points along the MSB Ladder. These eight tap
points are then connected to the eight flash comparators.
For example, if the analog input signal applied to V
is be-
tween 0 and 3/16 of V
(V
= V
V
), the esti-
mator decoder instructs the comparator multiplexer to select
the eight tap points between 8/256 and 2/8 of V
and con-
nects them to the eight flash comparators. The first flash
conversion is now performed, producing the five MSBs of
data.
The remaining three LSBs are generated next using the
same eight comparators that were used for the first flash
conversion. As determined by the results of the MSB flash, a
voltage from the MSB Ladder equivalent to the magnitude of
DS011086-18
FIGURE 6. Block Diagram of the ADC08061/2 Multi-Step Flash Architecture
www.national.com
11
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| ADC08061CIWMX | 功能描述:IC CONVERTER A/D 8BIT 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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