參數(shù)資料
型號(hào)： ADAV803ASTZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/60頁(yè)
文件大小： 0K
描述： IC CODEC AUDIO R-DVD 3.3V 64LQFP
標(biāo)準(zhǔn)包裝： 1,500
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無(wú)
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 102 / 101
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
配用： EVAL-ADAV803EBZ-ND - BOARD EVALUATION FOR ADAV803
ADAV803
Rev. A | Page 35 of 60
Group Delay and Mute—Address 0001000 (0x08)
Table 29. Group Delay and Mute Register Bit Map
7
6
5
4
3
2
1
0
MUTE_SRC
GRPDLY6
GRPDLY5
GRPDLY4
GRPDLY3
GRPDLY2
GRPDLY1
GRPDLY0
Table 30. Group Delay and Mute Register Bit Descriptions
Bit Name
Description
MUTE_SRC
Soft-mutes the output of the sample rate converter.
0 = No mute.
1 = Soft mute.
GRPDLY[6:0]
Adds delay to the sample rate converter FIR filter by GRPDLY[6:0] input samples.
0000000 = No delay.
0000001 = 1 sample delay.
0000010 = 2 sample delay.
1111110 = 126 sample delay.
1111111 = 127 sample delay.
Receiver Configuration 1—Address 0001001 (0x09)
Table 31. Receiver Configuration 1 Register Bit Map
7
6
5
4
3
2
1
0
NOCLOCK
RxCLK1
RxCLK0
AUTO_DEEMPH
ERR1
ERR0
LOCK1
LOCK0
Table 32. Receiver Configuration 1 Register Bit Descriptions
Bit Name
Description
NOCLOCK
Selects the source of the receiver clock when the PLL is not locked.
0 = Recovered PLL clock is used.
1 = ICLK1 is used.
RxCLK[1:0]
Determines the oversampling ratio of the recovered receiver clock.
00 = RxCLK is a 128 × fS recovered clock.
01 = RxCLK is a 256 × fS recovered clock.
10 = RxCLK is a 512 × fS recovered clock.
11 = Reserved.
AUTO_DEEMPH
Automatically de-emphasizes the data from the receiver based on the channel status information.
0 = Automatic de-emphasis is disabled.
1 = Automatic de-emphasis is enabled.
ERR[1:0]
Defines what action the receiver should take, if the receiver detects a parity or biphase error.
00 = No action is taken.
01 = Last valid sample is held.
10 = Invalid sample is replaced with zeros.
11 = Reserved.
LOCK[1:0]
Defines what action the receiver should take, if the PLL loses lock.
00 = No action is taken.
01 = Last valid sample is held.
10 = Zeros are sent out after the last valid sample.
11 = Soft-mute of the last valid audio sample.
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