參數(shù)資料
型號: ADAU1381BCBZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 60/84頁
文件大小: 0K
描述: IC AUDIO CODEC STEREO LN 30WLCSP
標準包裝: 1
類型: 立體聲音頻
數(shù)據(jù)接口: 串行,SPI?
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標準 ADC / DAC (db): 97 / 100
動態(tài)范圍,標準 ADC / DAC (db): 96.5 / 100
電壓 - 電源,模擬: 1.8 V ~ 3.65 V
電壓 - 電源,數(shù)字: 1.63 V ~ 3.65 V
工作溫度: -25°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 30-UFBGA,WLCSP
供應商設備封裝: 30-WLCSP(3.4x2.64)
包裝: 標準包裝
配用: EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
其它名稱: ADAU1381BCBZ-RL7DKR
ADAU1381
Rev. B | Page 63 of 84
PLAYBACK PATH CONFIGURATION
Register 16412 (0x401C), Playback Mixer Left Control
Bit 5, Left DAC Mute
This bit mutes the left DAC output. It does not have any slew
and is updated immediately when the register write has been
completed. This results in an abrupt cutoff of the audio output
and should therefore be preceded by a soft mute in the sound
engine or a slew mute using the DAC attenuator.
Bits[4:1], Left Playback Beep Gain
These bits set the gain of the beep signal in the left playback
path. If the zero-crossing detector is activated, the change in
gain is applied on the next detected zero crossing or when the
timeout period expires, whichever comes first. The gain control
is in 3 dB increments and should not be incremented more than
3 dB at a time in order to avoid audible artifacts on the output.
Register 16414 (0x401E), Playback Mixer Right Control
Bit 6, Right DAC Mute
This bit mutes the right DAC output. It does not have any slew
and is updated immediately when the register write has been
completed. This results in an abrupt cutoff of the audio output
and should therefore be preceded by a soft mute in the sound
engine or a slew mute using the DAC attenuator.
Bits[4:1], Right Playback Beep Gain
These bits set the gain of the beep signal in the right playback
path. If the zero-crossing detector is activated, the change in
gain is applied on the next detected zero crossing or when the
timeout period expires, whichever comes first. The gain control
is in 3 dB increments and should not be incremented more than
3 dB at a time in order to avoid audible artifacts on the output.
Table 47. Playback Mixer Left Control Register
Bits
Description
Default
[7:6]
Reserved
5
Left DAC mute
0
0: muted
1: unmuted
[4:1]
Left playback beep gain
0000
0000: muted
0001: 15 dB
0010: 12 dB
0011: 9 dB
0100: 6 dB
0101: 3 dB
0110: 0 dB
0111: +3 dB
1000: +6 dB
0
Reserved
Table 48. Playback Mixer Right Control Register
Bits
Description
Default
7
Reserved
6
Right DAC mute
0
0: muted
1: unmuted
5
Reserved
[4:1]
Right playback beep gain
0000
0000: muted
0001: 15 dB
...
1000: +6 dB
0
Reserved
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