參數(shù)資料
型號: AD9956YCPZ
廠商: Analog Devices Inc
文件頁數(shù): 17/32頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER 1.8V 48LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 14 b
主 fclk: 3GHz
調(diào)節(jié)字寬(位): 48 b
電源電壓: 1.71 V ~ 1.96 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
配用: AD9956-VCO/PCBZ-ND - BOARD EVAL 14BIT 1.8V 48LFCSP
AD9956/PCBZ-ND - BOARD EVAL FOR AD9956
AD9956
Rev. A | Page 24 of 32
REGISTER MAP AND DESCRIPTION
Table 5.
Register
Name
(Serial
Address)
Bit
Range
(MSB) Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value/
Profile
<31:24>
Open1
Open1
Open1
PLL Lock
Error
0x00
<23:16>
LOAD SRR @
I/O_UPDATE
Auto-Clr
Frequency
Accum.
Auto-
Clr
Phase
Accum.
Enable
Sine
Output
Clear
Frequency
Accum.
Clear
Phase
Accum.
Linear
Sweep
Enable
Linear
Sweep
No Dwell
0x00
<15:8>
LSB First
SDI/O
Input
Only
Open1
Open1
Open1
0x00
Control
Function
Register 1
(CFR1)
(0x00)
<7:0>
Digital
Power-
Down
PFD Input
Power-
Down
PLLREF
Crystal
Enable
SYNC_CLK
Disable
Auto Sync
Multiple
AD9956s
Software
Manual
Sync
Hardware
Manual
Sync
High
Speed
Sync
Enable
0x00
<39:32>
DAC
Power-
Down
Open1
Open1
Internal
Band Gap
Power-
Down
Internal
CML
Driver
DRV_RSET
0x00
<31:24>
Clock Driver Rising Edge <31:29>
Clock Driver Falling Edge Control
<28:26>
PLL Lock
Detect
Enable
PLL Lock
Detect
Mode
0x00
<23:16>
RF Divider
Power-
Down
RF Divider Ratio
<22:21>
Clock
Driver
Power-
Down
Clock Driver Input
Select <19:18>
Slew Rate
Control
RF Div
REFCLK
Mux Bit
0x78
<15:8>
Divider N Control <15:12>
Divider M Control <11:8>
0x00
Control
Function
Register 2
(CFR2)
(0x01)
<7:0>
Open1
CP
Polarity
CP
Full PD
CP
Quick PD
CP Current Scale <2:0>
0x07
<23:16>
Rising Delta Frequency Tuning Word <23:16>
0x00
<15:8>
Rising Delta Frequency Tuning Word <15:8>
0x00
Rising Delta
Frequency
Tuning
Word
(RDFTW)
(0x02)
<7:0>
Rising Delta Frequency Tuning Word <7:0>
0x00
<23:16>
Falling Delta Frequency Tuning Word <23:16>
0x00
<15:8>
Falling Delta Frequency Tuning Word <15:8>
0x00
Falling Delta
Frequency
Tuning
Word
(FDFTW)
(0x03)
<7:0>
Falling Delta Frequency Tuning Word <7:0>
0x00
<15:8>
Rising Sweep Ramp Rate <15:8>
0x00
Rising
Sweep
Ramp Rate
(RSRR)
(0x04)
<7:0>
Rising Sweep Ramp Rate <7:0>
0x00
<15:8>
Rising Sweep Ramp Rate <15:8>
0x00
Falling
Sweep
Ramp Rate
(FSRR)
(0x05)
<7:0>
Rising Sweep Ramp Rate <7:0>
0x00
1 In all cases, open bits must be written to 0.
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