參數(shù)資料
型號(hào)： AD9956YCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/32頁(yè)
文件大?。?/td> 0K
描述： IC SYNTHESIZER 1.8V 48LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 3GHz
調(diào)節(jié)字寬（位）： 48 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
配用： AD9956-VCO/PCBZ-ND - BOARD EVAL 14BIT 1.8V 48LFCSP
AD9956/PCBZ-ND - BOARD EVAL FOR AD9956
AD9956
Rev. A | Page 21 of 32
Automatic Synchronization
In automatic synchronization mode, the device is placed into
slave mode and automatically aligns the internal SYNC_CLK to
a master SYNC_CLK signal, supplied on the SYNC_IN input.
When this bit is enabled, the PLL_LOCK is not available as an
output, however, an out-of-lock condition can be detected by
reading Control Function Register 1 and checking the status of
the PLL_LOCK_ERROR bit, CFR1<24>. The automatic
synchronization function is enabled by setting the Control
Function Register 1 automatic synchronization bit, CFR1<3>.
To employ this function at higher clock rates (SYNC_CLK >
62.5 MHz and SYSCLK > 250 MHz), the high speed sync
enable bit (CFR1<0>) should be set as well.
Manual Synchronization, Hardware Controlled
In this mode, the user controls the timing relationship of the
SYNC_CLK with respect to SYSCLK. When hardware manual
synchronization is enabled, the PLL_LOCK/ SYNC_IN pin
becomes a digital input. For each and every rising edge detected
on the SYNC_IN input, the device advances the SYNC_IN
rising edge by one SYSCLK period. When this bit is enabled, the
PLL_LOCK is not available as an output. However, an out-of-
lock condition can be detected by reading Control Function
Register 1 and checking the status of the PLL Lock Error bit,
CFR1<24>. This synchronization function is enabled by setting
the hardware manual synchronization enable bit, CFR1<1>.
Manual Synchronization, Software Controlled
In this mode, the user controls the timing relationship between
SYNC_CLK and SYSCLK through software programming.
When the software manual synchronization bit (CFR1<2>) is
set high, the SYNC_CLK is advanced by one SYSCLK cycle.
Once this operation is complete, the bit is cleared. The user can
set this bit repeatedly to advance the SYNC_CLK rising edge
multiple times. Because the operation does not use the
PLL_LOCK/ SYNC_IN pin as a SYNC_IN input, the
PLL_LOCK signal can be monitored on the PLL_LOCK pin
during this operation.
SYSCLK DUT 1
SYNC CLK
DUT1
SYNC CLK DUT2 WITHOUT
SYNC_CLK ALIGNED
SYSCLK DUT 2
SYNCHRONIZATION FUNCTIONS CAN ALIGN DIGITAL CLOCK
RELATIONSHIPS, THEY CANNOT DESKEW THE EDGES OF CLOCKS
SYNC CLK DUT2 WITH
SYNC_CLK ALIGNED
01
2
30
01
2
3
04806-0-003
Figure 28. Synchronization Functions: Capabilities and Limitations
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