參數(shù)資料
型號: AD9911/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 43/44頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9911
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源: AD9911 Eval Brd Schematics
AD9911 Eval Brd BOM
AD9911 Eval Brd Gerber Files
標(biāo)準(zhǔn)包裝: 1
系列: AgileRF™
主要目的: 計時,直接數(shù)字合成(DDS)
已用 IC / 零件: AD9911
已供物品:
相關(guān)產(chǎn)品: AD9911BCPZ-REEL7-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP
AD9911BCPZ-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP
AD9911
Rev. 0 | Page 8 of 44
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DATA LATENCY (PIPELINE DELAY) SINGLE-
TONE MODE2, 3
Frequency, Phase, and Amplitude Words to
DAC Output with Matched Latency Enabled
29
SYSCLK
cycles
Frequency Word to DAC Output with
Matched Latency Disabled
29
SYSCLK
cycles
Phase Offset Word to DAC Output with
Matched Latency Disabled
25
SYSCLK
cycles
Amplitude Word to DAC Output with
Matched Latency Disabled
17
SYSCLK
cycles
DATA LATENCY (PIPELINE DELAY)
MODULATION MODE4
Frequency Word to DAC Output
34
SYSCLK
Cycles
Phase Offset Word to DAC Output
29
SYSCLK
Cycles
Amplitude Word to DAC Output
21
SYSCLK
Cycles
DATA LATENCY (PIPELINE DELAY) LINEAR
SWEEP MODE4
Frequency Rising/Falling Delta Tuning Word
to DAC Output
41
SYSCLK
Cycles
Phase Offset Rising/Falling Delta Tuning
Word to DAC Output
37
SYSCLK
Cycles
Amplitude Rising/Falling Delta Tuning Word
to DAC Output
29
SYSCLK
Cycles
1 For the VCO frequency range of 160 MHz to 255 MHz, the appropriate setting for the VCO gain bit is dependent upon supply, temperature and process. Therefore, in a
production environment this frequency band must be avoided.
2 Data latency is reference to the I/O_UPDATE pin.
3 Data latency is fixed and the units are system clock (SYSCLK) cycles
4 Data latency is referenced to a profile change.
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