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參數(shù)資料
| 型號： | AD9911/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/44頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9911 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | AD9911 Eval Brd Schematics AD9911 Eval Brd BOM AD9911 Eval Brd Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9911 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9911BCPZ-REEL7-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP AD9911BCPZ-ND - IC DDS 500MSPS DAC 10BIT 56LFCSP |
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AD9911
Rev. 0 | Page 24 of 44
05
78
5-
05
5
0
MUX
1
PHASE SWEEP EN
PHASE
ACCUMULATOR
PHASE OFFSET
ADDER
CPW0
0
MUX
1
FREQ SWEEP EN
CTW0
AMP SWEEP EN
ACR
Z–1
COS(X)
RU/RD LOGIC
SWEEP FUNCTION LOGIC
DAC
32
15
10
01
MUX
Figure 41. Linear Sweep Capability
Setting the Rate of the Linear Sweep
The rate of the linear sweep is set by the intermediate step size
(delta-tuning word) between S0 and E0 (see Figure 42) and the
time spent (sweep ramp rate word) at each step. The resolution
of the delta-tuning word is 32 bits for frequency, 14 bits for
phase, and 10 bits for amplitude. The resolution for the delta
ramp rate word is 8 bits.
In linear sweep, the user programs a rising delta word (RDW,
Register 0x08) and a rising sweep ramp rate word (RSRR,
Register 0x07). These settings apply when sweeping from F0 to
E0. The falling delta word (FDW, Register 0x09) and falling
sweep ramp rate (FSRR, Register 0x07) apply when sweeping
from E0 to S0.
When programming, note that attention is required to prevent
overflow of the sweep. If the sweep accumulator is allowed to
overflow, an uncontrolled, continuous sweep operation occurs.
To avoid this, the magnitude of the rising or falling delta word
should be smaller than the difference between full scale and the
E0 value (full scale E0). For a frequency sweep, full scale is
2311. For a phase sweep, full scale is 214 1. For an amplitude
sweep, full scale is 2101.
The graph in Figure 42 displays a linear sweep up and then
down using a profile pin. Note that the no dwell bit is cleared. If
the no dwell bit (CFR<15>) is set, the sweep accumulator
returns to 0 upon reaching E0. For more information, see the
Linear Sweep No Dwell Mode section.
(F
RE
Q
UE
NCY
/P
HAS
E
/A
M
P
L
IT
UDE
)
L
INE
AR
S
W
E
P
RDW
RSRR
FSRR
Δf,p,a
FDW
TIME
SO
EO
PROFILE PIN
Δf,p,a
Δt
05
78
5-
0
40
Figure 42. Linear Sweep Mode
For a piecemeal or a nonlinear transition between S0 and E0,
the delta tuning words and ramp rate words can be repro-
grammed during the transition.
The formulae for calculating the step size of RDW or FDW are
CLK
SYNC
RDW
f
_
2
32
×
=
Δ
(Hz)
°
×
=
360
2
14
RDW
ΔΦ
×
=
Δ
10
2
RDW
a
DAC full-scale current
The formula for calculating delta time from RSRR or FSRR is
(
)
(
_
/
Hz
CLK
SYNC
RSRR
t =
Δ
At 500 MSPS operation (SYNC_CLK =125 MHz), the
minimum time interval between steps is 1/125 MHz × 1 = 8 ns.
The maximum time interval is (1/125 MHz) × 255 = 2.04 μs.
Frequency Linear Sweep Example
This section provides an example of a frequency linear sweep
followed by a description.
AFP CFR<23:22> =10, modulation level FR1<9:8> = 00, sweep
enable CFR<14> = 1, linear sweep no-dwell CFR<15> = 0.
In linear sweep mode, when the profile pin transitions from low
to high, the RDW is applied to the input of the sweep accumu-
lator and the RSRR register is loaded into the sweep rate timer.
The RDW accumulates at the rate given by the ramp rate
(RSRR) until the output equals the CTW1 register value. The
sweep is then complete and the output held constant in
frequency.
When the profile pin transitions from high to low, the FDW is
applied to the input of the sweep accumulator and the FSRR
register is loaded into the sweep rate timer.
The FDW accumulates at the rate given by the ramp rate
(FSRR) until the output equals the CTW0 register value. The
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| AD9912 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer w/ 14-bit DAC |
| AD9912/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 1 GSPS Direct Digital Synthesizer W/ 14-Bit DAC 制造商:Analog Devices 功能描述:EVAL KIT FOR 1 GSPS DIRECT DGTL SYNTHESIZER W/ 14BIT DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION BOARD AD9912 1GSPS DDS |
| AD9912A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9912 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9912ABCPZ | 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9912ABCPZ-REEL7 | 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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