參數(shù)資料
型號: AD9887
廠商: Analog Devices, Inc.
英文描述: Dual Interface for Flat Panel Displays
中文描述: 雙接口的平板顯示器
文件頁數(shù): 7/40頁
文件大?。?/td> 321K
代理商: AD9887
REV. 0
AD9887
–7–
Table I. Complete Pinout List
P
in
Type
Pin
Name
Pin
Number
Function
Value
Interface
Analog Video
Inputs
R
AIN
G
AIN
B
AIN
HSYNC
VSYNC
SOGIN
CLAMP
COAST
CKEXT
CKINV
Analog Input for Converter R
Analog Input for Converter G
Analog Input for Converter B
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
119
110
100
Analog
Analog
Analog
External
Sync/Clock
Inputs
Horizontal SYNC Input
Vertical SYNC Input
Input for Sync-on-Green
Clamp Input (External CLAMP Signal)
PLL COAST Signal Input
External Pixel Clock Input (to Bypass the PLL) to V
DD
or Ground
ADC Sampling Clock Invert
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
82
81
108
93
84
83
94
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Sync Outputs
HSOUT
VSOUT
SOGOUT
HSYNC Output Clock (Phase-Aligned with DATACK)
VSYNC Output Clock (Phase-Aligned with DATACK)
Sync on Green Slicer Output
Internal Reference Output (Bypass with 0.1
μ
F to Ground)
Reference Input (1.25 V
±
10%)
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
139
138
140
Both
Both
Analog
Voltage
Reference
REFOUT
REFIN
1.25 V
1.25 V
±
10%
126
125
Analog
Analog
Clamp Voltages
R
MIDSC
V
R
CLAMP
V
G
MIDSC
V
G
CLAMP
V
B
MIDSC
V
B
CLAMP
V
FILT
Red Channel Midscale Clamp Voltage Output
Red Channel Midscale Clamp Voltage Input
Green Channel Midscale Clamp Voltage Output
Green Channel Midscale Clamp Voltage Input
Blue Channel Midscale Clamp Voltage Output
Blue Channel Midscale Clamp Voltage Input
120
118
111
109
101
99
Analog
Analog
Analog
Analog
Analog
Analog
0.0 V to 0.75 V
0.0 V to 0.75 V
0.0 V to 0.75 V
PLL Filter
Connection for External Filter Components for Internal PLL
78
Analog
Power Supply
V
D
V
DD
PV
D
GND
Analog Power Supply
Output Power Supply
PLL Power Supply
Ground
3.3 V
±
10%
3.3 V
±
10%
3.3 V
±
10%
0 V
Both
Both
Both
Both
Serial Port
(2-Wire
Serial Interface)
SDA
SCL
A0
A1
Serial Port Data I/O
Serial Port Data Clock (100 kHz Max)
Serial Port Address Input 1
Serial Port Address Input 2
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
92
91
90
89
Both
Both
Both
Both
Data Outputs
Red B[7:0]
Green B[7:0]
Blue B[7:0]
Red A[7:0]
Green A[7:0]
Blue A[7:0]
Port B/Odd Outputs of Converter “Red,” Bit 7 Is the MSB
Port B/Odd Outputs of Converter “Green,” Bit 7 Is the MSB
Port B/Odd Outputs of Converter “Blue,” Bit 7 Is the MSB
Port A/Even Outputs of Converter “Red,” Bit 7 Is the MSB
Port A/Even Outputs of Converter “Green,” Bit 7 Is the MSB
Port A/Even Outputs of Converter “Blue,” Bit 7 Is the MSB
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
153–160
13–20
33–40
143–150
3–10
23–30
Both
Both
Both
Both
Both
Both
Data Clock
Outputs
DATACK
DATACK
Data Output Clock for the Analog and Digital Interface
Data Output Clock Complement for the Analog Interface Only
3.3 V CMOS
3.3 V CMOS
134
135
Both
Both
Sync Detect
S
CDT
SCAN
IN
SCAN
OUT
SCAN
CLK
NC
Sync Detect Output
3.3 V CMOS
136
Both
Scan Function
Input for SCAN Function
Output for SCAN Function
Clock for SCAN Function
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
129
45
50
Both
Both
Both
No Connect
These Pins Should be Left Unconnected
71–73
Both
Digital Video
Data Inputs
R
x0
+
R
x0
R
x1
+
R
x1
R
x2
+
R
x2
R
xc
+
R
xc
Digital Input Channel 0 True
Digital Input Channel 0 Complement
Digital Input Channel 1 True
Digital Input Channel 1 Complement
Digital Input Channel 2 True
Digital Input Channel 2 Complement
62
63
59
60
56
57
Digital
Digital
Digital
Digital
Digital
Digital
Digital Video
Clock Inputs
Digital Data Clock True
Digital Data Clock Complement
65
66
Digital
Digital
Data Enable
DE
Data Enable
3.3 V CMOS
137
Digital
Control Bits
CTL[0:3]
Decoded Control Bits
3.3 V CMOS
46–49
Digital
R
TERM
R
TERM
Sets Internal Termination Resistance
53
Digital
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