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參數(shù)資料
| 型號(hào)： | AD9877ABSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 28/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR FRONT END 100MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 1.17W |
| 電壓 - 電源，模擬： | 3.3V |
| 電壓 - 電源，數(shù)字： | 3.3V |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-MQFP（14x20） |
| 包裝： | 托盤 |
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AD9877
Rev. B | Page 34 of 36
SIGNAL ROUTING
The digital Rx and Tx signal paths should be kept as short as
possible. Also, these traces should have a controlled impedance
of about 50 Ω. This prevents poor signal integrity and the high
currents that can occur during undershoot or overshoot caused
by ringing. If the signal traces cannot be kept shorter than
approximately 1.5 inches, then series termination resistors
(33 Ω to 47 Ω) should be placed close to all signal sources. It is a
good idea to series terminate all clock signals at their source
regardless of trace length.
The receive (I IN, Q IN, and RF IN) signals are the most
sensitive signals on the board. Careful routing of these signals is
essential for good receive path performance. The Rx± signals
form a differential pair and should be routed together as a pair.
By keeping the traces adjacent to each other, noise coupled onto
the signals appears as common-mode and is largely rejected by
the MxFE receive input. Keeping the driving point impedance
of the receive signal low and placing any low-pass filtering of
the signals close to the MxFE further reduces the possibility of
noise corrupting these signals.
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