- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375249 > AD9865BCPZRL1 (Analog Devices, Inc.) Broadband Modem Mixed-Signal Front End PDF資料下載
參數(shù)資料
| 型號： | AD9865BCPZRL1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | 寬帶調(diào)制解調(diào)器混合信號前端 |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | AD9865BCPZRL1 |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
AD9865
SERIAL PORT TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 5.
Parameter
WRITE OPERATION (See Figure 46)
SCLK Clock Rate (f
SCLK
)
SCLK Clock High (t
HI
)
SCLK Clock Low (t
LOW
)
SDIO to SCLK Setup Time (t
DS
)
SCLK to SDIO Hold Time (t
DH
)
SEN to SCLK Setup Time (t
S
)
SCLK to SEN Hold Time (t
H
)
READ OPERATION (See Figure 47 and Figure 48)
SCLK Clock Rate (f
SCLK
)
SCLK Clock High (t
HI
)
SCLK Clock Low (t
LOW
)
SDIO to SCLK Setup Time (t
DS
)
SCLK to SDIO Hold Time (t
DH
)
SCLK to SDIO (or SDO) Data Valid Time (t
DV
)
SEN to SDIO Output Valid to Hi-Z (t
EZ
)
Rev. A | Page 7 of 48
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
14
14
14
0
14
0
14
14
14
0
Typ
2
Max
32
32
14
Unit
MHz
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 6.
Parameter
READ OPERATION
1
(See Figure 50)
Output Data Rate
Three-State Output Enable Time (t
PZL
)
Three-State Output Disable Time (t
PLZ
)
Rx Data Valid Time (t
VT
)
Rx Data Output Delay (t
OD
)
WRITE OPERATION (See Figure 49)
Input Data Rate (1× Interpolation)
Input Data Rate (2× Interpolation)
Input Data Rate (4× Interpolation)
Tx Data Setup Time (t
DS
)
Tx Data Hold Time (t
DH
)
Latch Enable Time (t
EN
)
Latch Disable Time (t
DIS
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
II
II
II
II
II
II
II
II
II
II
II
II
Min
5
1.5
20
10
5
1
2.5
Typ
Max
80
3
3
4
80
80
50
3
3
Unit
MSPS
ns
ns
ns
ns
MSPS
MSPS
MSPS
ns
ns
ns
ns
1
C
LOAD
= 5 pF for digital data outputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9865CHIPS | Broadband Modem Mixed-Signal Front End |
| AD9887 | Dual Interface for Flat Panel Displays |
| AD9888 | 100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888KS-100 | 100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888KS-140 | TRI N PLUG F 2-13 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9865CHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9865-EB | 制造商:Analog Devices 功能描述:MODEM, BROADBAND MODEM MIXED SGNL FRONT END - Bulk |
| AD9866 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9866BCP | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:12BIT MIXED SIGNAL CONVERTER 9866 |
| AD9866BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。