參數(shù)資料
型號(hào)： AD9865BCPZRL1
廠商： Analog Devices, Inc.
英文描述： Broadband Modem Mixed-Signal Front End
中文描述： 寬帶調(diào)制解調(diào)器混合信號(hào)前端
文件頁(yè)數(shù)： 2/48頁(yè)
文件大?。?/td> 1672K
代理商： AD9865BCPZRL1
AD9865
Rev. A | Page 2 of 48
TABLE OF CONTENTS
Specifications.....................................................................................3
Tx Path Specifications..................................................................3
Rx Path Specifications..................................................................4
Power Supply Specifications.......................................................5
Digital Specifications...................................................................6
Serial Port Timing Specifications...............................................7
Half-Duplex Data Interface (ADIO Port) Timing
Specifications................................................................................7
Full-Duplex Data Interface (Tx and Rx Port) Timing
Specifications................................................................................8
Explanation of Test Levels...........................................................8
Absolute Maximum Ratings............................................................9
Thermal Characteristics..............................................................9
ESD Caution..................................................................................9
Pin Configuration and Function Descriptions...........................10
Typical Performance Characteristics...........................................12
Rx Path Typical Performance Characteristics........................12
TxDAC Path Typical Performance Characteristics...............16
IAMP Path Typical Performance Characteristics..................18
Serial Port ........................................................................................19
Register Map Description .........................................................21
Serial Port Interface (SPI) .........................................................21
Digital Interface..............................................................................23
Half-Duplex Mode.....................................................................23
Full-Duplex Mode......................................................................24
RxPGA Control..........................................................................25
TxPGA Control..........................................................................27
Transmit Path..................................................................................28
Digital Interpolation Filters......................................................28
TxDAC and IAMP Architecture.............................................. 28
Tx Programmable Gain Control.............................................. 30
TxDAC Output Operation........................................................ 30
IAMP Current-Mode Operation.............................................. 30
IAMP Voltage-Mode Operation .............................................. 31
IAMP Current Consumption Considerations........................ 32
Receive Path.................................................................................... 33
Rx Programmable Gain Amplifier........................................... 33
Low-Pass Filter........................................................................... 34
Analog-to-Digital Converter (ADC)....................................... 35
AGC Timing Considerations.................................................... 36
Clock Synthesizer........................................................................... 37
Power Control and Dissipation.................................................... 39
Power-Down............................................................................... 39
Half-Duplex Power Savings...................................................... 39
Power Reduction Options......................................................... 40
Power Dissipation...................................................................... 42
Mode Select upon Power-Up and Reset.................................. 42
Analog and Digital Loop-Back Test Modes............................ 43
PCB Design Considerations.......................................................... 44
Component Placement.............................................................. 44
Power Planes and Decoupling.................................................. 44
Ground Planes............................................................................ 44
Signal Routing ............................................................................ 44
Evaluation Board............................................................................ 46
Outline Dimensions....................................................................... 47
Ordering Guide.......................................................................... 47
REVISION HISTORY
11/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Specifications Tables.................................................... 3
Changes to Serial Table..................................................................19
Changes to Full Duplex Mode section.........................................24
Change to TxDAC and IAMP Architecture section..................29
Change to TxDAC Output Operation section............................ 30
Insert equation................................................................................ 37
Change to Figure 84 caption......................................................... 42
11/03—Revision 0: Initial Version
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