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參數(shù)資料
| 型號： | AD9865BCPZRL1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | 寬帶調(diào)制解調(diào)器混合信號前端 |
| 文件頁數(shù)： | 6/48頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | AD9865BCPZRL1 |
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AD9865
Parameter
POWER CONSUMPTION (Half-Duplex Operation with f
DATA
= 50 MSPS)
2
Tx Mode
I
AVDD
+ I
CLKVDD
I
DVDD
+ I
DRVDD
Rx Mode
I
AVDD
+ I
CLKVDD
I
DVDD
+ I
DRVDD
POWER CONSUMPTION OF FUNCTIONAL BLOCKS
1
(I
AVDD
+ I
CLKVDD
)
RxPGA and LPF
ADC
TxDAC
IAMP (Programmable)
Reference
CLK PLL and Synthesizer
MAXIMUM ALLOWABLE POWER DISSIPATION
STANDBY POWER CONSUMPTION
IS_TOTAL (Total Supply Current)
POWER DOWN DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and synthesizer
POWER UP DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and Synthesizer
Rev. A | Page 6 of 48
Temp
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Test Level
IV
IV
IV
IV
III
III
III
III
III
III
IV
III
III
III
III
III
III
III
III
III
III
Min
10
Typ
112
46
225
36.5
87
108
38
170
107
13
440
12
20
20
27
7.8
88
13
20
20
Max
130
49.5
253
39
120
1.66
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
W
mA
ns
ns
ns
ns
ns
μs
ns
μs
ns
μs
1
Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP’s current consumption, which is application dependent.
2
Default power-up settings for MODE = LOW and CONFIG = LOW.
DIGITAL SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; R
SET
= 2 k, unless otherwise noted.
Table 4.
Parameter
Temp
CMOS LOGIC INPUTS
High Level Input Voltage
Full
Low Level Input Voltage
Full
Input Leakage Current
Input Capacitance
Full
CMOS LOGIC OUTPUTS (C
LOAD
= 5 pF)
High Level Output Voltage (I
OH
= 1 mA)
Full
Low Level Output Voltage (I
OH
= 1 mA)
Full
Output Rise/Fall Time (High Strength Mode and C
LOAD
= 15 pF)
Full
Output Rise/Fall Time (Low Strength Mode and C
LOAD
= 15 pF)
Full
Output Rise/Fall Time (High Strength Mode and C
LOAD
= 5 pF)
Full
Output Rise/Fall Time (Low Strength Mode and C
LOAD
= 5 pF)
Full
RESET
Minimum Low Pulse Width (Relative to f
ADC
)
Test Level
VI
VI
VI
VI
VI
VI
VI
VI
VI
Min
DRVDD – 0.7
DRVDD – 0.7
1
Typ
3
1.5/2.3
1.9/2.7
0.7/0.7
1.0/1.0
Max
0.4
12
0.4
Unit
V
V
μA
pF
V
V
ns
ns
ns
ns
Clock
cycles
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