參數(shù)資料
型號: AD9856
廠商: ANALOG DEVICES INC
元件分類: 衰減器
英文描述: CMOS 180 MHz Quadrature Digital Upconverter(時鐘頻率為180MHz,CMOS的積分上變頻器)
中文描述: RF/MICROWAVE UP CONVERTER
文件頁數(shù): 9/19頁
文件大?。?/td> 244K
代理商: AD9856
AD9856 Preliminary Technical Information
9
This Advanced Datasheet describes a product which is in the development stage. Specifications and pin-out are subject to change without notice. For additional information please contact Analog Devices,
High-speed Converter Group, 7910 Triad Center Drive, Greensboro, NC, 27409 Tel: 336/605-4365
REV. 6/2/98
N1, N2 - Bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer
cycle of the communications cycle.
A4, A3, A2, a1, A0 - Bits 4, 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data
transfer portion of the communications cycle. For multi-byte transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD9856. See the MSB/LSB transfer section for details.
Table IV
N1
0
0
1
1
N0
0
1
0
1
Description
transfer 1 byte
transfer 2 bytes
transfer 3 bytes
transfer 4 bytes
Serial Interface Port Pin Description
The AD9856 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry
standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats,
including both the Motorola 6905/11 SPI and Intel 8051 SSR protocols. The serial port can be configured as either a
2-wire or 3-wire hardware interface. The 2-wire operation performs read/write operations on the SDIO pin.
The 3-wire operation performs writes on SDIO and reads data out on the SDO pin.
Definition of serial interface port pins:
SCLK - Serial Clock. The serial clock pin is used to synchronize data to and from the AD9856 and to run the internal
state machines. SCLK maximum frequency is 5 MHz.
CS(Bar) - Chip Select (Bar). Active low input that allows more than one device on the same serial communications
lines. The SDO and SDIO pins will go to a high impedance state when this input is high. If driven high during any
communications cycle, that cycle is suspended until CS is reactivated low. Chip Select can be tied low in systems that
maintain control of SCLK.
SDIO - Serial Data I/O. Data is always written into the AD9856 on this pin. However, this pin can be used as a
bidirectional data line. The configuration of this pin is controlled by the REG0<7> bit. REG0<7> defaults to logic
zero, which configures the SDIO pin as bidirectional.
SDO - Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving
data. In the case where the AD9856 operates in a single bidirectional I/O mode, this pin does not output data and is set
to a high impedance state.
CA CLK - Output clock pin to the AD8320. If using the AD8320 programmable cable driver amplifier and desire the
AD9856 to program its gain control register, connect this pin to the CLK input of the AD8320. See the Writing the
AD8320 Gain Control Register section for details.
CA Data - Output data pin to the AD8320. If using the AD8320 programmable cable driver amplifier and desire the
AD9856 to program its gain control register, connect this pin to the SDATA input of the AD8320. See the Writing the
AD8320 Gain Control Register section for details.
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