
AD9856 Preliminary Technical Information
3
This Advanced Datasheet describes a product which is in the development stage. Specifications and pin-out are subject to change without notice. For additional information please contact Analog Devices,
High-speed Converter Group, 7910 Triad Center Drive, Greensboro, NC, 27409 Tel: 336/605-4365
REV. 6/2/98
AD9856 ELECTRICAL CHARACTERISTICS
(Vs=+3.3V
±
5%, Rset=3.9 k
, Reference Clock
Frequency = 8.0 MHz with internal PLL enabled @ 20X).
Parameter
Temp
Test Level
AD9856
Min Typ Max
Units
CMOS LOGIC INPUTS
Logic "1" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
Input Capacitance
POWER SUPPLY
+Vs Current @ Full Operating Conditions
P
DISS
@ Full Operating Conditions
P
DISS
@ Non-Bursting
P
DISS
@ Full Power-down Mode
+25°C
+25°C
+25°C
+25°C
+25°C
I
I
+2.7
V
V
uA
uA
pF
+0.4
12
12
IV
IV
V
3
+25°C
+25°C
+25°C
+25°C
I
I
I
I
121
400
40
1
mA
mW
mW
mW
NOTES
1Absolute maximum ratings are limiting values, to be
applied individually, and beyond which the serviceability
of the circuit may be impaired. Functional operability
under any of these conditions is not necessarily implied.
Exposure of absolute maximum rating conditions for
extended periods of time may affect device reliability.
2
DC to 70 MHz output bandwidth.
3
Residual phase noise
4
Excluding aliased frequency components
EXPLANATION OF TEST LEVELS
Test Level
I -
III -
IV -
V -
VI -
+25°C. 100% production tested at temperature
extremes for military temperature
devices; guaranteed by design and
characterization testing for industrial devices.
100% Production Tested.
Sample Tested Only.
Parameter is guaranteed by design and
characterization testing.
Parameter is a typical value only.
All devices are 100% production tested at
Table I. MODULATOR FUNCTION DESCRIPTION
Input Data Format
12-bit parallel, 6-bit nibble, 3-bit nibble - selectable via control bus. Input data
is assumed to be 4X oversampled when input to the AD9856.
Min: CLK/512; max: 45 MS/s. Programmable via control bus.
For 5-70 MHz Aout operation (160 MHz internal reference clock):
w/PLL enabled: 8 - 20 MHz, programmable via control bus
w/PLL disabled: 160 MHz
Note: For optimum data synchronization, the AD9856 Reference Clock, and
the input data clock, should be derived from the same clock source.
Programmable in integer steps over the range of 4X-20X; enable/disable
control via control bus
Four pin-selectable, pre-programmed, modulator formats
Fixed 4X, programmable 2X, and programmable 64X
Interpolating filters that compensate for CIC passband rolloff characteristics
When Burst Mode is enabled via the control bus, the rising edge of the applied
Tx Enable pulse should be coincident with, and frame, the input data packet.
This establishes data sampling synchronization.
When continuous mode is enabled via the control bus, the Tx Enable pin
becomes the I/Q demux control. Logic “1” outputs the demux to the I channel;
logic “0” outputs the demux to the Q channel.
Pre-compensates for SINX/X roll-off of DAC; user bypassable.
COS - j SIN or COS + j SIN, selectable via control bus
Input Sample Rate
Input Reference Clock Frequency
Internal Reference Clock PLL
Profile Select
Interpolating range
Halfband Filters
Tx Enable Function - Burst Mode
Tx Enable Function - Continuous Mode
SINX/X filter
I/Q Channel Invert