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參數(shù)資料
| 型號： | AD9856 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 衰減器 |
| 英文描述： | CMOS 180 MHz Quadrature Digital Upconverter(時鐘頻率為180MHz,CMOS的積分上變頻器) |
| 中文描述： | RF/MICROWAVE UP CONVERTER |
| 文件頁數(shù)： | 5/19頁 |
| 文件大小： | 244K |
| 代理商： | AD9856 |
AD9856 Preliminary Technical Information
5
This Advanced Datasheet describes a product which is in the development stage. Specifications and pin-out are subject to change without notice. For additional information please contact Analog Devices,
High-speed Converter Group, 7910 Triad Center Drive, Greensboro, NC, 27409 Tel: 336/605-4365
REV. 6/2/98
Table III. Control Bus Register Definitions.
Bit name
Width
Position
Description
Profile
Address
(Hex)
00
SDO Active
1
<7>
Active high indicates serial port uses
dedicated in/out lines. Default low
configures serial port as single line
I/O.
Active high indicates serial port access
is LSB to MSB format. Default low
indicates MSB to LSB format.
Reference clock multiplier
Enable automatic power down between
bursts
This bit adjusts output selection of the
CIC filters. Allows user to gain up the
output when interpolation rates are not
a power of two.
Continuous mode operation enabled.
Uses Tx enable pin to synchronize I/Q
data: 1=I, 0=Q. Operates only in 12-bit
parallel word format.
Active high full sleep mode bit.
Active high FSK mode. DDS cosine
data output.
Inverse SINC filter bypassed in data
path.
Bypass the REFCLK PLL
Input format select bits: 1x - full word
mode, 01 - half-word mode, 00 -
quarter word mode.
32-bit DDS frequency tuning word
N/A
LSB First
1
<6>
N/A
00
REFCLK<4:0>
PD
5
1
<5:1>
<0>
N/A
N/A
00
00
MoreGain
1
<7>
N/A
01
Continuous Mode
1
<6>
N/A
01
SLEEP
FSK Mode
1
1
<5>
<4>
N/A
N/A
01
01
By pass Inverse
SINC Filter
BPLL
INFMT
1
<3>
N/A
01
1
2
<2>
<1:0>
N/A
N/A
01
01
FTW1<31:0>
32
<7:0>
<7:0>
<7:0>
<7:0>
<7:2>
1
05, 04,
03, 02
INT1<5:0>
6
Interpolation rate bits: these bits
program the interpolation rate of the
first interpolator. Available rates are 1-
64.
Spectral inversion bit: Active high
enables the spectral inversion
capability of the AD9856.
Bypass third half-band filter
AD8320 gain control bits: Sets the
AD8320 line driver gain control data
to be output at the dedicated control
bus.
32-bit frequency tuning word
1
06
SI1
1
<1>
1
06
BPHB3
GS1<7:0>
1
8
<0>
<7:0>
1
1
06
07
FTW2<31:0>
32
<7:0>
<7:0>
<7:0>
<7:0>
2
0B, 0A,
09, 08
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